WM8971L Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8971L Datasheet PDF : 56 Pages
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Advanced Information
CONTROL INTERFACE TIMING – 3-WIRE MODE
CSB
SCLK
tCSL
tSCY
tSCH
tSCL
tSCS
tCSH
tCSS
WM8971L
SDIN
tDSU
tDHO
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
SYMBOL
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tPS
MIN
TYP
MAX
UNIT
80
ns
200
ns
80
ns
80
ns
40
ns
40
ns
40
ns
40
ns
40
ns
5
ns
w
AI Rev 3.0 March 2004
15
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