WM8976 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8976

Stereo CODEC With Speaker Driver

Wolfson Microelectronics plc 

Pre-Production

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

tMCLKL

tMCLKH

tMCLKY

WM8976

Figure 2 System Clock Timing Requirements

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC

PARAMETER

System Clock Timing Information

MCLK cycle time

MCLK duty cycle

Note 1:

SYMBOL

TMCLKY

TMCLKDS

CONDITIONS

MCLK=SYSCLK (=256fs)

MCLK input to PLL Note 1

MIN

81.38

20

60:40

TYP

MAX

40:60

PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.

UNIT

ns

ns

AUDIO INTERFACE TIMING – MASTER MODE

Figure 3 Digital Audio Data Timing – Master Mode (see Control Interface)

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PP Rev 3.0 April 2006

15

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