XRT72L52(2001) Просмотр технического описания (PDF) - Exar Corporation

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XRT72L52
(Rev.:2001)

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

Exar Corporation 

XRT72L52

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. P1.1.3

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PRELIMINARY

TERFACE BLOCK .................................................................................................................................... 329

Figure 150. Illustration of the Terminal Equipment being interfaced to the Receive Payload Data Input In-

terface Block of the XRT72L52 Framer IC (Serial Mode Operation) ................................................... 330

Figure 151. An Illustration of the behavior of the signals between the Receive Payload Data Output Inter-

face block of the XRT72L52 and the Terminal Equipment .................................................................. 331

Figure 152. Illustration of the XRT72L52 DS3/E3 Framer IC being interfaced to the Receive Section of the

Terminal Equipment (Nibble-Parallel Mode Operation) ....................................................................... 332

Figure 153. Illustration of the signals that are output via the Receive Payload Data Output Interface block

(for Nibble-Parallel Mode Operation). .................................................................................................. 333

5.3.6 Receive Section Interrupt Processing ................................................................................................... 333

BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ...................................................................... 334

RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 334

RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 335

RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 335

RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 336

RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 336

RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ......................................................... 336

RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 337

RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 337

RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 338

RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 338

RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................ 339

RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 339

RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................. 340

RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................. 340

RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 340

RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................. 341

RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................. 341

RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................. 342

RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................. 342

RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................ 342

RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................ 343

6.0 E3/ITU-T G.832 Operation of the XRT72L52 ..................................................................................... 344

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 344

6.1 DESCRIPTION OF THE E3, ITU-T G.832 FRAMES AND ASSOCIATED OVERHEAD BYTES ........................................ 344

Figure 154. Illustration of the E3, ITU-T G.832 Framing Format. ....................................................... 344

6.1.1 Definition of the Overhead Bytes ........................................................................................................... 344

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 345

TABLE 69: DEFINITION OF THE TRAIL TRACE BUFFER BYTES, WITHIN THE E3, ITU-T G.832 FRAMING FORMAT

345

THE MAINTENANCE AND ADAPTATION (MA) BYTE FORMAT ........................................................................ 346

TABLE 70: A LISTING OF THE VARIOUS PAYLOAD TYPE VALUES AND THEIR CORRESPONDING MEANING ... 347

6.2 THE TRANSMIT SECTION OF THE XRT72L52 (E3 MODE OPERATION) .................................................................. 347

Figure 155. A Simple Illustration of the Transmit Section, within the XRT72L52, when it has been configured

to operate in the E3 Mode ................................................................................................................... 348

6.2.1 The Transmit Payload Data Input Interface Block ................................................................................. 348

Figure 156. A Simple Illustration of the Transmit Payload Data Input Interface Block ....................... 349

TABLE 71: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT IN-

TERFACE ............................................................................................................................................... 350

Figure 157. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-

terface block of the XRT72L52 for Mode 1 (Serial/Loop-Timed) Operation ........................................ 352

Figure 158. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Interface

block of the XRT72L52 and the Terminal Equipment (for Mode 1 Operation) .................................... 353

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 353

Figure 159. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-

XIV

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