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XRT72L58

EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

Exar Corporation 

XRT72L58

EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. P1.1.2

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PRELIMINARY

PIN DESCRIPTION

PIN DESCRIPTION FOR THE XRT72L58

PIN #

PIN NAME

TYPE

DESCRIPTION

A1

TxNib3[7]/

TxHDLCDat3[7]

I

Transmit Nibble-Parallel Payload Data Input -3, Channel 7:

If the Nibble-Parallel Mode has been selected, the Terminal Equipment is

expected to input data, that is intended to be transmitted to the remote termi-

nal, over an E3 or DS3 transport medium. The Framer will take data, applied

to this pin (along with TxNib1, TxNib2, and TxNib3), and insert it into an out-

bound "E3 or DS3" frame. The XRT72L58 will sample the data that is at these

input pins, upon the rising edge of the "TxNibClk" signal.

Transmit HDLC Data Input - 3:

This pin accepts bit 3 TxHDLC data when the HDLC controller is turned on.

A2

TxNibClk[7]/

SndFCS[7]

O

Transmit Nibble Clock Signal:

When the XRT72L58 is configured in the “Nibble-Parallel” mode, this clock

signal can be derived from either the “TxInClk” or the “RxLineClk” signal

(depending upon which signal is selected as the timing reference).

The user is advised to configure the Terminal Equipment to output the “out-

bound” payload data (to the XRT72L58 Framer) onto the “TxNib[3:0]” input

pins, upon the rising edge of this clock signal.

NOTES:

1. For DS3 applications, the XRT72L58 Framer will output 1176 clock

edges (to the Terminal Equipment) for each “outbound” DS3 frame.

2. For E3, ITU-T G.832 applications, the XRT72L58 Framer will output

1074 clock edges (to the Terminal Equipment) for each “outbound” E3

frame.

3. For E3, ITU-T G.751 applications, the XRT72L58 Framer will output

384 clock edges (fo the Terminal Equipment) for each “outbound” E3

frame.

Send Frame Check Sequence:

I

When the HDLC controller is turned on, this pin is driven “high” during the

time when FCS bytes are being sent after a valid HDLC message.

A3

TxNib0[7]/

TxHDLCDat0[7]

I

Transmit Nibble-Parallel Payload Data Input -0:

The Terminal Equipment is expected to input data, that is intended to be

transmitted to the remote terminal, over an E3 or DS3 transport medium. The

Framer will take data, applied to this pin (along with TxNib1, TxNib2, and

TxNib3), and insert it into an outbound "E3 or DS3" frame. The XRT72L58 will

sample the data that is at these input pins, upon the rising edge of the "TxNib-

Clk" signal.

NOTE: This input pin is active only if the Nibble-Parallel Mode has been

selected.

Transmit HDLC Data Input - 0:

This pin accepts bit 0 TxHDLC data when the HDLC controller is turned on.

A4

TxOHFrame[7]

TxHDLCClk[7]

O

Transmit Overhead Framing Pulse:

This output pin pulses "high" when the Transmit Overhead Data Input Inter-

face block is expecting the first Overhead bit, within a DS3 or E3 frame to be

applied to the TxOH input pin.

This pin is "high" for one clock period of TxOHClk.

Transmit HDLC Output Clock:

When the HDLC controller is on, TxHDLCDat is updated by the 72L58 by this

clock signal.

3

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