Block Diagram
LC73860
Pin Functions
Number
1
2
3
4
5
Name
INPUT
PD
OSCI
VSS
SD
6
ACK
7
EST
8
VDD
I/O
Description
I Input coupling capacitor connection. Biased internally to VDD/2.
I Power-down mode is selected when HIGH.
I 4.194304MHz external clock input.
Ground (0V).
O Outputs the 4-bit serial, decoded DTMF output, least significant bit first.
Shift data to SD control.
I Four pulses are used to output the 4-bit DTMF code. Before the first rising edge, the
data is latched into the shift register.
O
Indicates the presence of a DTMF signal when HIGH. This pin can be monitored and
after a short delay, data can be accessed by applying 4 pulses to ACK.
O 4.5 to 5.5V supply voltage.
Test/Application Circuit
No.4367–3/5