AT88SC102-09PT-00 Просмотр технического описания (PDF) - Unspecified

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AT88SC102-09PT-00

1K EEPROM– Security Logic with Two Application Zones

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Figure 18-8. Erase Operation Application Zone 2 (AZ2) EC2 Function Enabled

Reset

Read

Compare EZ2

(A)

Address Ax

A0

A1

A2 A735

A736 A737

A766

A767

Read SCAC

(B)

A768

A769

A770

Write

(C)

A771

Read

(D)

Erase

(E)

Read

(F)

(G)

A772

RST

CLK

I/O

DX

D0

D1

Output

PGM

CD736 CD737

Input

CD767

00

0

Output

10

01

Input Input Output Input

0

D772

Output

E2 flag

Notes:

1. An = Internal Address, Dn = Read data (output), CDn = Compare data (input).

2. EC2EN fuse = 1 (enabled)

3. Security Level 2 (issuer fuse blown)

A = Compare sequence of the Application Zone 2 Erase Key (EZ2).

B =This diagram shows an example in which the first three bits of the EC2 Erase Counter (bits 1280 – 1282) are previously

set to “0”. The write/erase operation should be performed on the first bit in EC2 which is found to be a “1”. Bit 1283 in this

example is a “1”, so the write/erase sequence is begun with that bit.

C = Write operation of a “0” over the existing “1”.

D = The AT88SC102 will output a “0” following the write operation. If the comparison is successful, the E2 flag is set and the

AZ2 zone can be erased.

E = Erase operation.

F = The AT88SC102 will output a “0” following the erase operation regardless of the success of the compare operation.

G = On the falling edge of CLK, the address is incremented and the state of the next bit is driven on the I/O pin.

24 AT88SC102

1419C–SMEM–6/08

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