ADAU1401AWBSTZ Просмотр технического описания (PDF) - Analog Devices
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ADAU1401AWBSTZ Datasheet PDF : 52 Pages
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ADAU1401A
DIGITAL TIMING SPECIFICATIONS
Table 8.
Parameter1
MASTER CLOCK
tMP
tMP
tMP
tMP
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
tSIS
tSIH
tLOS
tLOH
tTS
tSODS
tSODM
SPI PORT
fCCLK
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCDS
tCDH
tCOD
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tBFT
MULTIPURPOSE PINS AND RESET
tGRT
tGFT
tGIL
tRLPW
Limit
tMIN
tMAX
Unit Description
36
244
ns
MCLKI period, 512 × fS mode.
48
366
ns
MCLKI period, 384 × fS mode.
73
488
ns
MCLKI period, 256 × fS mode.
291
1953
ns
MCLKI period, 64 × fS mode.
40
ns
INPUT_BCLK low pulse width.
40
ns
INPUT_BCLK high pulse width.
10
ns
INPUT_LRCLK setup; time to INPUT_BCLK rising.
10
ns
INPUT_LRCLK hold; time from INPUT_BCLK rising.
10
ns
SDATA_INx setup; time to INPUT_BCLK rising.
10
ns
SDATA_INx hold; time from INPUT_BCLK rising.
10
ns
OUTPUT_LRCLK setup in slave mode.
10
ns
OUTPUT_LRCLK hold in slave mode.
5
ns
OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew.
40
ns
SDATA_OUTx delay in slave mode; time from OUTPUT_BCLK falling.
40
ns
SDATA_OUTx delay in master mode; time from OUTPUT_BCLK falling.
6.25
MHz CCLK frequency.
80
ns
CCLK pulse width low.
80
ns
CCLK pulse width high.
0
ns
CLATCH setup; time to CCLK rising.
100
ns
CLATCH hold; time from CCLK rising.
80
ns
CLATCH pulse width high.
0
ns
CDATA setup; time to CCLK rising.
80
ns
CDATA hold; time from CCLK rising.
101
ns
COUT delay; time from CCLK falling.
400
kHz SCL frequency.
0.6
μs
SCL high.
1.3
μs
SCL low.
0.6
μs
SCL setup time, relevant for repeated start condition.
0.6
μs
SCL hold time. After this period, the first clock is generated.
100
ns
Data setup time.
300
ns
SCL rise time.
300
ns
SCL fall time.
300
ns
SDA rise time.
300
ns
SDA fall time.
0.6
Bus-free time; time between stop and start.
50
ns
GPIO rise time.
50
ns
GPIO fall time.
1.5 × 1/fS μs
GPIO input latency; time until high/low value is read by core.
20
ns
RESET low pulse width.
1 All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 66).
Rev. A | Page 7 of 52
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