AD712JNZ Просмотр технического описания (PDF) - Analog Devices

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AD712JNZ

Dual Precision, Low Cost,High Speed, BiFET Op Amp

Analog Devices 

AD712

OPTIMIZING SETTLING TIME

Most bipolar high-speed D/A converters have current outputs;

therefore, for most applications, an external op amp is required

for current-to-voltage conversion. The settling time of the con-

verter/op amp combination depends on the settling time of the

DAC and output amplifier. A good approximation is:

tS Total = (tS DAC )2 + (tS AMP )2

The settling time of an op amp DAC buffer will vary with the

noise gain of the circuit, the DAC output capacitance, and with

the amount of external compensation capacitance across the

DAC output scaling resistor.

Settling time for a bipolar DAC is typically 100 ns to 500 ns.

Previously, conventional op amps have required much longer

settling times than have typical state-of-the-art DACs; therefore,

the amplifier settling time has been the major limitation to a

high-speed voltage-output D-to-A function. The introduction of

the AD711/AD712 family of op amps with their 1 µs (to ± 0.01%

of final value) settling time now permits the full high-speed

capabilities of most modern DACs to be realized.

In addition to a significant improvement in settling time, the

low offset voltage, low offset voltage drift, and high open-loop

gain of the AD711/AD712 family assures 12-bit accuracy over

the full operating temperature range.

The excellent high-speed performance of the AD712 is shown in

the oscilloscope photos of Figure 25. Measurements were taken

using a low input capacitance amplifier connected directly to the

summing junction of the AD712 – both photos show the worst

case situation: a full-scale input transition. The DAC’s 4 kΩ

[10 kΩ||8 kΩ = 4.4 kΩ] output impedance together with a

10 kΩ feedback resistor produce an op amp noise gain of 3.25.

The current output from the DAC produces a 10 V step at the

op amp output (0 to –10 V Figure 25a, –10 V to 0 V Figure

25b.)

Therefore, with an ideal op amp, settling to ± 1/2 LSB (± 0.01%)

requires that 375 µV or less appears at the summing junction.

This means that the error between the input and output (that

voltage which appears at the AD712 summing junction) must be

less than 375 µV. As shown in Figure 25, the total settling time

for the AD712/AD565 combination is 1.2 microseconds.

0.1␮F

R2

GAIN 100⍀

ADJUST

REF

IN

REF

GND

REF

OUT

+

10V

–

19.95k⍀

20k⍀

BIPOLAR

OFFSET ADJUST

R1

VCC

100⍀ BIPOLAR

OFF

20V

SPAN

AD565A

0.5mA

9.95k⍀

IREF

DAC

IOUT = 4 ؋

IO

IREF ؋ CODE

5k⍀

5k⍀

10V

SPAN

DAC

OUT

8k⍀

10pF +15V

0.1␮F

1/2

AD712

0.1␮F

OUTPUT

–10V TO +10V

–VEE

0.1␮F

POWER

GND

MSB

LSB

–15V

Figure 24. ±10 V Voltage Output Bipolar DAC

1mV

5V

100

90

SUMMING

JUNCTION

0V

10

0%

–10V

OUTPUT

500ns

1mV

5V

100

90

SUMMING

JUNCTION

0V

10

0%

–10V

OUTPUT

500ns

a. (Full-Scale Negative Transition)

b. (Full-Scale Positive Transition)

Figure 25. Settling Characteristics for AD712 with AD565A

REV. B

–7–

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