ADSP-2141LKS-N1 Просмотр технического описания (PDF) - Analog Devices

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ADSP-2141LKS-N1

Safe Net® DSP

Analog Devices 

ADSP-2141L

IDMA Mode Multiplex Bus Pin Definition

IDMA Port (218x Mode)

PIN FUNCTION DESCRIPTIONS—IDMA Mode Multiplex Bus

Pin Name

IDMA Name

Pins

I/O

MPLX5

IRD

1

I

MPLX6

IWR

1

I

MPLX7

IS

1

I

MPLX8

IAL

1

I

MPLX9

IACK

1

O

MPLX10

FL0

1

O

MPLX11

FL1

1

O

MPLX12

FL2

1

O

MPLX_BUS

IAD

16

I/O

Description

IDMA Port Read Input

IDMA Port Write Input

IDMA Port Select

IDMA Port Address Latch

IDMA Port Access Ready Acknowledge

Output Flags

Output Flags

Output Flags

IDMA Data I/O

PCI Port

PIN FUNCTION DESCRIPTIONS—PCI Mode Multiplex Bus

Pin Name

PCI Name

Pins

I/O

MPLX1

Pci_cbe3

1

I/O

MPLX2

Pci_cbe2

1

I/O

MPLX3

Pci_cbe1

1

I/O

MPLX4

Pci_cbe0

1

I/O

MPLX5

Pci_idsel

1

I

MPLX6

Pci_gnt

1

I

MPLX7

Pci_frame

1

I/O

MPLX8

Pci_devsel

1

I/O

MPLX9

Pci_trdy

1

I/O

MPLX10

Pci_perr

1

I/O

MPLX11

Pci_serr

1

I/O

MPLX12

Pci_req

1

O

MPLX_BUS

Pci_ad15:0

Pci_ad31:16

32

I/O

PF7/INT_H

Pci_intA

1

O

Description

Bus Command / Byte Enable 3

Bus Command / Byte Enable 2

Bus Command / Byte Enable 1

Bus Command / Byte Enable 0

Initialization Device Select

Bus Grant

Cycle Frame

Device Select

Target Ready

Parity Error

System Error

PCI Bus Request

PCI Address/Data Bus

PCI Interrupt A Request

SYSTEM INTERFACE

The ADSP-2141L may be integrated into a wide variety of sys-

tems, including those that already have a microprocessor and

those that will use the ADSP-2141L as the main processor. The

device can be configured into one of two Host Bus modes:

IDMA or PCI.

IDMA Bus Mode

The IDMA bus mode operates the same as in a native ADSP-

218x device, as described in this section.

The IDMA port provides an efficient means of communication

between a host system and the ADSP-2141L. The port is used

to access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. The IDMA

port cannot, however, be used to write to the DSP’s memory-

mapped control registers.

The IDMA port has a 16-bit multiplexed address and data bus,

and supports reading or writing 16-bit data (DM) or 24-bit

program memory (PM). The IDMA port is completely asyn-

chronous and can be written to while the ADSP-2141L is oper-

ating at full speed.

The DSP memory address is latched and then automatically

incremented after each IDMA transaction. An external device can

therefore access a block of sequentially addressed memory by

specifying only the starting address of the block. This increases

throughput as the address does not have to be sent for each

memory access.

The IDMA port access occurs in two phases. The first is the

IDMA address latch cycle. When the acknowledge is asserted, a

14-bit address and 1-bit destination type can be driven onto the

bus by an external device. The address specifies an on-chip

memory location; the destination type specifies whether it is a

DM or PM access. The falling edge of the address latch signal

latches this value to the IDMAA register.

Once the address is stored, data can either be read from or

written to the ADSP-2141L’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2141L that a particular

transaction is required. In either case, there is a one-processor-

cycle delay for synchronization. The memory access consumes

an additional processor cycle.

Once an access has occurred, the latched address is automati-

cally incremented and another access can occur.

Through the IDMAA register, the ADSP-2141L can also

specify the starting address and data format for DMA operation.

Figure 6 illustrates a typical system configuration for the

IDMA mode.

REV. 0

–11–

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