ADUC814ARU-REEL Просмотр технического описания (PDF) - Analog Devices
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ADUC814ARU-REEL Datasheet PDF : 72 Pages
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ADuC814
TIMING SPECIFICATIONS1,2,3
Table 34. Clock Input (External Clock Driven XTAL1)
AVDD = 2.7 V to 3.3 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.3 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted
32.768 kHz External Crystal
Parameter
Min
Typ
Max
Unit
tCK
tCKL
tCKH
tCKR
tCKF
1/tCORE
tCORE
tCYC
XTAL1 Period
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC814 Core Clock Frequency4
ADuC814 Core Clock Period5
ADuC814 Machine Cycle Time6
30.52
µs
15.16
µs
15.16
µs
20
ns
20
ns
0.131
16.78
MHz
0.476
µs
0.72
5.7
91.55
µs
1 AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1, and at 0.45 V for a Logic 0. Timing measurements are made at VIH min for a Logic 1, and at VIL max for a
Logic 0 as shown in Figure 61.
2 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded VOH/VOL level occurs as shown in Figure 61.
3 CLOAD for all outputs = 80 pF, unless otherwise noted.
4 ADuC814 internal PLL locks onto a multiple (512 times) the external crystal frequency of 32.768 kHz to provide a stable 16.777216 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5 This number is measured at the default Core_Clk operating frequency of 2.09 MHz.
6 ADuC814 Machine Cycle Time is nominally defined as 12/Core_CLK.
tCKH
tCKR
DVDD – 0.5V
0.45V
tCKL
tCKF
tCK
Figure 60. XTAL1 Input
0. 2DV DD + 0. 9V
TEST POINTS
0. 2DV DD – 0. 1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINT
Figure 61. Timing Waveform Characteristics
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
Rev. A | Page 64 of 72
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