GAL22V10D-15LJN Просмотр технического описания (PDF) - Lattice Semiconductor

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GAL22V10D-15LJN

High Performance E2CMOS PLD Generic Array Logic™

Lattice Semiconductor 

SpSepceifcicifaictaiotinosnsGGALA2L22V21V01D0

AC Switching Characteristics

Over Recommended Operating Conditions

PARAM.

TEST

COND.1

DESCRIPTION

tpd

A Input or I/O to Comb. Output

tco

A Clock to Output Delay

tcf2

— Clock to Feedback Delay

tsu

— Setup Time, Input or Fdbk before Clk↑

th

— Hold Time, Input or Fdbk after Clk↑

A Maximum Clock Frequency with

External Feedback, 1/(tsu + tco)

COM / IND COM / IND

IND

COM / IND

-10

-15

-20

-25

UNITS

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

1 10 3 15 3 20 3 25 ns

1 7 2 8 2 10 2 15 ns

— 2.5 — 2.5 — 8 — 13 ns

6—

0—

83.3 —

10 — 12 — 15 —

0— 0 — 0 —

55.5 — 41.6 — 33.3 —

ns

ns

MHz

fmax3

A

Maximum Clock Frequency with

Internal Feedback, 1/(tsu + tcf)

110 — 80 — 45.4 — 35.7 — MHz

A Maximum Clock Frequency with

No Feedback

twh

— Clock Pulse Duration, High

twl

— Clock Pulse Duration, Low

ten

B Input or I/O to Output Enabled

tdis

C Input or I/O to Output Disabled

tar

A Input or I/O to Asynch. Reset of Reg.

tarw — Asynch. Reset Pulse Duration

tarr

— Asynch. Reset to Clk↑ Recovery Time

tspr

— Synch. Preset to Clk↑ Recovery Time

125 — 83.3 — 50 — 38.5 — MHz

4 — 6 — 10 — 13 — ns

4 — 6 — 10 — 13 — ns

1 10 3 15 3 20 3 25 ns

1 9 3 15 3 20 3 25 ns

1 13 3 20 3 25 3 25 ns

8 — 15 — 20 — 25 — ns

8 — 10 — 20 — 25 — ns

8 — 10 — 14 — 15 — ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL

PARAMETER

CI

Input Capacitance

CI/O

I/O Capacitance

*Characterized but not 100% tested.

MAXIMUM*

8

8

UNITS

pF

pF

TEST CONDITIONS

VCC = 5.0V, VI = 2.0V

VCC = 5.0V, VI/O = 2.0V

8

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