K3919 Просмотр технического описания (PDF) - Renesas Electronics
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K3919 Datasheet PDF : 8 Pages
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2SK3919
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
VDS = 25 V, VGS = 0 V
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
Gate Cut-off Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(off)
| yfs |
RDS(on)1
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 16 A
VGS = 10 V, ID = 32 A
RDS(on)2 VGS = 5.0 V, ID = 16 A
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Ciss
Coss
Crss
VDS = 10 V
VGS = 0 V
f = 1 MHz
Turn-on Delay Time
Rise Time
Turn-off Delay Time
td(on)
tr
td(off)
VDD = 12.5 V, ID = 32 A
VGS = 10 V
RG = 10 Ω
Fall Time
tf
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage Note
QG
QGS
QGD
VF(S-D)
VDD = 20 V
VGS = 10 V
ID = 64 A
IF = 64 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
trr
IF = 64 A, VGS = 0 V
Qrr
di/dt = 100 A/µs
Note Pulsed
MIN.
2.0
9.7
TYP.
2.5
19
4.5
6.8
2050
460
330
16
19
53
22
42
8
15
0.97
23
11
MAX.
10
±100
3.0
5.6
13.7
UNIT
µA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
RG
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
90%
VGS
90%
10% 10%
tr td(off)
tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D17078EJ4V0DS
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