MK10DN512ACMC7 Просмотр технического описания (PDF) - Freescale Semiconductor

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производитель

MK10DN512ACMC7

K10 Sub-Family

Freescale Semiconductor 

Peripheral operating requirements and behaviors

Table 15. MCG specifications (continued)

Symbol Description

Min.

FLL

ffll_ref

fdco

FLL reference frequency range

DCO output

frequency range

Low range (DRS=00)

640 × ffll_ref

Mid range (DRS=01)

31.25

20

40

1280 × ffll_ref

Mid-high range (DRS=10)

60

1920 × ffll_ref

High range (DRS=11)

80

fdco_t_DMX32 DCO output

frequency

2560 × ffll_ref

Low range (DRS=00)

—

732 × ffll_ref

Mid range (DRS=01)

—

1464 × ffll_ref

Mid-high range (DRS=10)

—

2197 × ffll_ref

High range (DRS=11)

—

Jcyc_fll

tfll_acquire

FLL period jitter

2929 × ffll_ref

• fDCO = 48 MHz

• fDCO = 98 MHz

FLL target frequency acquisition time

—

—

—

PLL

fvco

VCO operating frequency

Ipll

PLL operating current

• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

48.0

—

Ipll

PLL operating current

• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

—

2 MHz, VDIV multiplier = 24)

fpll_ref PLL reference frequency range

2.0

Jcyc_pll PLL period jitter (RMS)

• fvco = 48 MHz

—

• fvco = 100 MHz

—

Typ.

Max.

—

20.97

39.0625

25

41.94

50

62.91

75

83.89

100

23.99

—

47.97

—

71.99

—

95.98

—

180

—

150

—

—

1

—

100

1060

—

600

—

—

4.0

120

—

50

—

Jacc_pll

PLL accumulated jitter over 1µs (RMS)

• fvco = 48 MHz

• fvco = 100 MHz

—

1350

—

—

600

—

Dlock

Dunl

Lock entry frequency tolerance

Lock exit frequency tolerance

± 1.49

—

± 4.47

—

Table continues on the next page...

± 2.98

± 5.97

Unit

kHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

ps

ms

MHz

µA

µA

MHz

ps

ps

ps

ps

%

%

Notes

2, 3

4, 5

6

7

7

8

8

K10 Sub-Family Data Sheet, Rev. 3, 6/2013.

28

Freescale Semiconductor, Inc.

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