MK10DN128AVLK5 Просмотр технического описания (PDF) - Freescale Semiconductor

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MK10DN128AVLK5

K10 Sub-Family

Freescale Semiconductor 

6. Cb = total capacitance of the one bus line in pF.

Peripheral operating requirements and behaviors

SDA

tf

SCL

tLOW

tr

tSU; DAT

tf

tHD; STA

tSP

tr

tBUF

S

tHD; STA

tHD; DAT

tHIGH

tSU; STA

SR

tSU; STO

P

S

Figure 24. Timing definition for fast and standard mode devices on the I2C bus

6.8.5 UART switching specifications

See General switching specifications.

6.8.6 SDHC specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

Table 43. SDHC switching specifications

Num

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8

Symbol

fpp

fpp

fpp

fOD

tWL

tWH

tTLH

tTHL

tOD

tISU

tIH

Description

Min.

Max.

Operating voltage

1.71

3.6

Card input clock

Clock frequency (low speed)

0

400

Clock frequency (SD\SDIO full speed\high speed)

0

25\50

Clock frequency (MMC full speed\high speed)

0

20\50

Clock frequency (identification mode)

0

400

Clock low time

7

—

Clock high time

7

—

Clock rise time

—

3

Clock fall time

—

3

SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SDHC output delay (output valid)

-5

8.3

SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SDHC input setup time

5

—

SDHC input hold time

0

—

Unit

V

kHz

MHz

MHz

kHz

ns

ns

ns

ns

ns

ns

ns

K10 Sub-Family Data Sheet, Rev. 3, 6/2013.

Freescale Semiconductor, Inc.

61

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