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IDT70T631S

HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

Integrated Device Technology 

HIGH-SPEED 2.5V

512/256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

PRELIMINARY

IDT70T633/1S

Features

◆ True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆ High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

◆ RapidWrite Mode simplifies high-speed consecutive write

cycles

◆ Dual chip enables allow for depth expansion without

external logic

◆ IDT70T633/1 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

◆ M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

◆ Busy and Interrupt Flags

Functional Block Diagram

◆ Full hardware support of semaphore signaling between

ports on-chip

◆ On-chip port arbitration logic

◆ Fully asynchronous operation from either port

◆ Separate byte controls for multiplexed bus and bus

matching compatibility

◆ Sleep Mode Inputs on both ports

◆ Supports JTAG features compliant to IEEE 1149.1 in

BGA-208 and BGA-256 packages

◆ Single 2.5V (±100mV) power supply for core

◆ LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

◆ Available in a 256-ball Ball Grid Array, 144-pin Thin Quad

Flatpack and 208-ball fine pitch Ball Grid Array

◆ Industrial temperature range (–40°C to +85°C) is available

for selected speeds

UBL

UBR

LBL

LBR

R/WL

CE0 L

CE1L

BB

BB

EE

EE

01

10

LL

RR

R/WR

CE0 R

CE1R

OEL

I/O0L- I/O17L

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

512/256K x 18

MEMORY

ARRAY

Din_L

Din_R

OER

I/O0R - I/O17R

A18L(1)

A0L

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

A18R (1)

A0R

CE0 L

CE1L

OEL

R/WL

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

OER

R/WR

TDI

TDO

CE0R

CE1R

BUSYL(2,3)

SEML

M/S

INTL(3)

NOTES:

ZZL(4)

ZZ

CONTROL

LOGIC

ZZR (4 )

1. Address A18x is a NC for IDT70T631.

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

3 BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

1

©2003 Integrated Device Technology, Inc.

TCK

JT AG

TMS

T R ST

BUSYR(2,3)

SEMR

INTR(3)

5670 drw 01

NOVEMBER 2003

DSC-5670/3

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