SL74HC4053
Figure 8. Swi tching Weveforms
* Includes all probe and jig capacitance.
Figure 9. Test Set-UP, Channel Select to Analog Out
Figure 10. Switching Weveforms
* Includes all probe and jig capacitance.
Figure 11. Test Set-UP, Analog In to Analog Out
Figure 12. Switching Weveforms
Figure 13. Test Set-UP, Enable to Analog Out
SLS
System Logic
Semiconductor