HC5503CM Просмотр технического описания (PDF) - Intersil

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HC5503CM

Low Cost 24V SLIC For PABX/Key Systems

Intersil 

HC5503

is the calculated value of 0.633 plus the feedback which is

1/4 TX (for matching to a 600Ω load, reference Equation 8).

The voltage at Rx is calculated in Equation 25.

RX = 0.633 – 14-- (0.633) = 0.474

(EQ. 25)

Substituting the values for TX and RX into Equation 24 and

setting the them equal to each other, the values of R3 and

R4 can then be determined.

-0---.R--6---43---3-- = 0----.R--4---37---4--

(EQ. 26)

Setting the value of R3 to 150kΩ sets the value of R4 to be

200kΩ.

Notice that the input voltage for the incoming signal (I1) is

taken at RX, instead of the conventional method at the

CODEC (point A, Figure 6). This alternative method is used

because the tolerance effects of R1 on the transhybrid

balance are eliminated.

R5

150kΩ R3

RX I1

R4 200kΩ

I2

R1

-

+

+

V0

A

-

+

R2

VIN

-

TX

CODEC/

FILTER

FIGURE 6. TRANSHYBRID CIRCUIT

Power Denial (PD)

Power denial limits power to the subscriber loop: it does not

power down the SLIC, i.e., the SLIC will still consume its

normal on-hook quiescent power during a power denial

period. This function is intended to “isolate” from the battery,

under processor control, selected subscriber loops during an

overload or similar fault status.

If PD is selected, the logic circuitry inhibits RC and switches in

a current source to C1. The capacitor charges up to a nominal

-3.5V at which point it is clamped. Since tip feed is always at

-4V, the battery feed across the loop is essentially zero, and

minimum loop power will be dissipated if the circuit goes off-

hook. No signalling functions are available during this mode.

After power denial is released (PD = 1), it will be several

hundred milliseconds (300ms) before the VRF output

reaches its nominal battery setting. This is due to the RC

time constant of R21 and C1.

The Logic Network

The logic network utilizes I2L logic. All external inputs and

outputs are LS TTL compatible: the relay driver is an open

collector output that can sink 60mA with a VCE of 1V.

Figure 9 is a schematic of the combination logic within the

network. The external inputs RC (Relay Control) and PD

(Power Denial) allow the switch controller to ring the line or

deny power to the loop, respectively. The Ring

Synchronization input (RS) facilitates switching of the ring

relay near a ring current zero crossing in order to minimize

inductive kickback from the telephone ringer.

Line Fault Protection

The subscriber loop can exist in a very hostile electrical

environment. It is often in close proximity to very high voltage

power lines, and can be subjected to lightning induced

voltage surges. The SLIC has to provide isolation between

the subscriber loop and the PBX/Key telephone system.

The most stringent line fault condition that the SLIC has to

withstand is that of the lightning induced surge.

The Intersil monolithic SLIC, in conjunction with a simple low

cost diode bridge, can achieve up to 450V of isolation

between the loop and switch. The level of isolation is a

function of the packaging technology and geometry together

with the chip layout geometries. One of the principal reasons

for using DI technology for fabricating the SLIC is that it

lends itself most readily to manufacturing monolithic circuits

for high voltage applications.

Figures 10 shows the application circuit for the HC5503. A

secondary protection diode bridge is indicated which

protects the feed amplifiers during a fault. Most line systems

will have primary protection networks. They often take the

form of a carbon block or arc discharge device. These limit

the fault voltage to less than 450V peak before it reaches the

line cards. Thus when a transient high voltage fault has

occurred, it will be transmitted as a wave front down the line.

The primary protection network must limit the voltage to

less than 450V. The attenuated wave front will continue

down the line towards the SLIC. The feed amplifier outputs

appear to the surge as very low impedance paths to the

system battery. Once the surge reaches the feed resistors,

fault current will flow into or out of the feed amplifier output

stages until the relevant protection diodes switch on. Once

the necessary diodes have started to conduct all the fault

current will be handled by them.

If the user wishes to characterize SLIC devices under

simulated high voltage fault conditions on the bench, he

should ensure that the negative battery power supply has

sufficient current capability to source the negative peak

fault current and low series inductance. If this is not the

case, then the battery supply could be pulled more

negative and destroy the SLIC if the total (VCC + VBAT)

voltage across it exceeds 75V.

10

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