MSC8122VT8000 Просмотр технического описания (PDF) - Freescale Semiconductor

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MSC8122VT8000

Quad Digital Signal Processor

Freescale Semiconductor 

Electrical Characteristics

2.5.5.3 DMA Data Transfers

Table 17 describes the DMA signal timing.

Table 17. DMA Signals

No.

Characteristic

37 DREQ set-up time before the 50% level of the falling edge of REFCLK

38 DREQ hold time after the 50% level of the falling edge of REFCLK

39 DONE set-up time before the 50% level of the rising edge of REFCLK

40 DONE hold time after the 50% level of the rising edge of REFCLK

41 DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge

Ref = CLKIN

Min Max

5.0

—

0.5

—

5.0

—

0.5

—

0.5

7.5

Ref = CLKOUT

(1.2 V only)

Min Max

5.0

—

0.5

—

5.0

—

0.5

—

0.5

8.4

Units

ns

ns

ns

ns

ns

The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ

according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction.

REFCLK

DREQ

38

37

40

39

DONE

41

DACK/DONE/DRACK

Figure 13. DMA Signals

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

27

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