PCF7341ATJ Просмотр технического описания (PDF) - NXP Semiconductors.
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PCF7341ATJ Datasheet PDF : 18 Pages
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NXP Semiconductors
Security Transponder and RISC Controller (STARC 2XLite)
Product Specification
PCF7x41ATJ
8 FUNCTIONAL DESCRIPTION
The PCF7x41ATJ incorporates Security Transponder and
Remote Keyless Entry features that are specified in detail
by the data sheet PCF7x41 and the corresponding ROM
Library Description; see section 13.
8.1 LF Field Power On Reset
When the transponder enters a LF Field a rectifier circuitry
becomes operational and the rectified voltage develops.
The LF Field has to be present for at least 2ms (tFLD,HLD)
before this supply voltage is passed on to become the
transponder supply voltage (VDDC). As soon as the supply
voltage (VDDC) exceeds the LF Field Power-On Reset
threshold voltage (VPOR,FLD) the device performs a chip
reset and starts its initialization sequence by executing its
boot routine, see Figure 4.
BTHR
t
LF Field applied
VPOR,FLD
VDDC
Invocation of device
BOOT Routine
tSTART
tFLD,HLD
tPOR-HLD
Figure 4 LF field power on reset timing
Subsequently, the transponder is muted and does not
respond to any command until termination of the device
boot sequence. The startup time, tSTART, depends on the
base station configuration, the resonance circuit properties
and the system coupling factor, however, is small
compared with the LF Field hold time (tFLD,HLD).
Regardless of the supply condition, once the supply voltage
(VDD) exceeds the Power On Reset threshold voltage
(VPOR,BAT respectively VPOR,FLD), POR becomes low.
After a short delay (TPOR,HLD), the flip-flop is forced into
latch state freezing the supply switch state and the RISC
Controller becomes operational. Program execution
commences starting with the BOOT Routine, before the
application Program or Transponder Emulation is being
invoked, see Figure 5
VPOR,FLD
VPOR,BAT
Invocation of
BOOT Routine
tPOR-HLD
tBOOT
Invocation of:
- Application Program or
- Transponder Emulation
t
Figure 5 Power-up timing
In order to force a LF Field Power-On Reset and proper
device initialization at any time, the LF field OFF condition
must be applied for at least tRESET,SETUP, in order to ensure
that the INTERNAL device supply voltage, VDDc, drops
below the threshold voltage (VPOR,FLD), see Figure 6.
VPOR,FLD
VDDC
LF field power on reset (POR)
threshold voltage
LF field OFF
t
tRESET_SETUP
Figure 6 LF field power on reset setup timing
2013 Oct 15
9
CONFIDENTIAL
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