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TC74HC697AF

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Toshiba 

TC74HC697AP/AF

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC697AP, TC74HC697AF

Synchronous Presettable 4-Bit Binary Up/Down Counter with Output Register (multiplexed

3-state outputs)

The TC74HC697A is high speed CMOS UP/DOWN

COUNTERS fabricated with silicon gate C2MOS technology.

It achieve the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

It counts on the rising edge of the Counter Clock (CCK) input

when “counter mode” is selected. If the up/down ( U/D ) input is

held high, the internal counter counts up. Conversely, if U/D is

held low, it counts down.

The internal counters outputs are latched into the output

registers on the rising edge of the Register Clock (RCK) input.

The outputs (QA~QD) are selected as either internal counter or

registered outputs by the output select ( R/C ) input. When high,

the outputs are counter outputs and when low, they are

registered outputs.

Two enable ( ENP , ENT ) inputs and a carry ( RCO ) output

are provided to enable cascading of the counters.

This facilitates easy implementation of n-bit counters without

using external gates.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

Features

• High speed: fmax = 38 MHz (typ.) at VCC = 5 V

• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C

• High noise immunity: VNIH = VNIL = 28% VCC (min)

• Outputs drive capability: 15 LSTTL loads for QA~QD

10 LSTTL loads for RCO

• Symmetrical output impedance:

|IOH| = IOL = 6 mA (min) for QA~QD

|IOH| = IOL = 4 mA (min) for RCO

• Balanced propagation delays: tpLH ∼− tpHL

• Wide operating voltage range: VCC (opr) = 2 to 6 V

• Pin and function compatible with 74LS697

TC74HC697AP

TC74HC697AF

Weight

DlP20-P-300-2.54A

SOP20-P-300-1.27A

: 1.30 g (typ.)

: 0.22 g (typ.)

Start of commercial production

1988-11

1

2014-03-01

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