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74LVC2G17 Просмотр технического описания (PDF) - NXP Semiconductors.

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74LVC2G17 Datasheet PDF : 19 Pages
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Nexperia
74LVC2G17
Dual non-inverting Schmitt trigger with 5 V tolerant input
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Fig 3. Logic diagram
7. Pinning information
7.1 Pinning
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PQE
/9&*
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*1' 
 9&&
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DDI
Fig 4. Pin configuration SOT363
and SOT457
/9&*
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*1' 
 9&&
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DDI
7UDQVSDUHQWWRSYLHZ
Fig 5. Pin configuration SOT886
/9&*
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*1' 
 9&&
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 <
DDI
7UDQVSDUHQWWRSYLHZ
Fig 6. Pin configuration SOT891,
SOT1115 and SOT1202
7.2 Pin description
Table 3. Pin description
Symbol
Pin
1A
1
GND
2
2A
3
2Y
4
VCC
5
1Y
6
8. Functional description
Description
data input
ground (0 V)
data input
data output
supply voltage
data output
Table 4.
Input
nA
L
H
Function table[1]
Output
nY
L
H
[1] H = HIGH voltage level; L = LOW voltage level.
74LVC2G17
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 15 December 2016
© Nexperia B.V. 2017. All rights reserved
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