MT8843AE Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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производитель
MT8843AE Datasheet PDF : 23 Pages
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MT8843
IN+ 1
IN- 2
GS 3
VRef 4
CAP 5
TRIGin 6
TRIGRC 7
TRIGout 8
MODE 9
OSCin 10
OSCout 11
VSS 12
24 VDD
23 St/GT
22 ESt
21 StD
20 INT
19 CD
18 DR
17 DATA
16 DCLK
15 FSKen
14 PWDN
13 IC
Pin Description
Figure 2 - Pin Connections
Pin # Name
Description
1
IN+ Non-inverting Input of the internal opamp.
2
IN- Inverting Input of the internal opamp.
3
GS Gain Select (Output) of internal opamp. It is recommended that the opamp be set to unity
gain. Refer to figure 7 for equation to calculate the closed loop opamp gain.
4
VRef Reference Voltage (Output). Nominally VDD/2. It is used to bias the input opamp.
5
CAP Capacitor. A 0.1µF decoupling capacitor should be connected across this pin and VSS.
6 TRIGin Trigger Input. Schmitt trigger buffer input. Used for line reversal and ring detection.
7 TRIGRC Trigger RC (Open Drain Output/Schmitt Input). Used to set the (RC) time interval from
TRIGin going low to TRIGout going high. An external resistor connected to VDD and
capacitor connected to VSS determines the duration of the (RC) time interval.
8 TRIGout Trigger Out (CMOS Output). Schmitt trigger buffer output. Used to indicate detection of
line reversal and/or ringing.
9 MODE 3-wire interface: Mode Select (CMOS Input). When low, selects interface mode 0.
When high, selects interface mode 1. See pin 16 (DCLK) description to understand how
MODE affects the DCLK pin.
10 OSCin Oscillator Input. A 3.579545MHz crystal should be connected between this pin and
OSCout. It may also be driven directly from an external clock source.
11 OSCout Oscillator Output. A 3.579545MHz crystal should be connected between this pin and
OSCin. When OSCin is driven by an external clock, this pin should be left open.
12
VSS Power Supply Ground.
13
IC Internal Connection. Must be connected to VSS for normal operation.
14 PWDN Power Down (Schmitt Input). Active high. When high, the device consumes minimal
power by disabling all functionality except TRIGin, TRIGRC and TRIGout. Must be pulled
low, for device operation.
15 FSKen FSK Enable (CMOS Input). Must be high for FSK demodulation. This pin should be set
low to prevent the FSK demodulator from reacting to extraneous signals (such as speech,
alert signal and DTMF which are all in the same frequency band as FSK).
16 DCLK 3-wire Interface: Data Clock (CMOS Input/Output). In mode 0 (MODE pin low), this pin
is an output. In mode 1 (MODE pin high), this pin is an input.
17 DATA 3-wire Interface: Data (CMOS Output). Mode 0 data appears at the pin once
demodulated. Mode 1 data is shifted out on the rising edge of the microcontroller
supplied DCLK.
5-32
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