ST7565-0B Просмотр технического описания (PDF) - Sitronix Technology Co., Ltd.
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производитель
ST7565-0B Datasheet PDF : 73 Pages
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ST7565S
ST7565S Pad Arrangement
Chip Size:
9,336μm x 1,000 μm
Bump Pitch:
58μm(Min.)
Bump Size:
PAD No. 001〜012
PAD No. 013〜102
PAD No. 103〜114
PAD No. 115
PAD No. 116〜128
PAD No. 129〜276
PAD No. 277〜289
PAD No. 290
Bump Height: 18μm(Typ)
Chip Thickness: 660μm
40μm x 90μm
56μm x 60μm
40μm x 90μm
102μm x 37.5μm
90μm x 40μm
40μm x 90μm
90μm x 40μm
102μm x 37.5μm
30um
39um
15 15
um um
15 15
um um
15 um
15 um
38um
30um
22um 30um 22um
114
115
．．．．．．．．
ST7565S
Y
PAD DIAGRAM
．
．
(0,0)
．
．
．
．
128
129
(-4558,-410)
38um 30um
13
(3528,395)
12
．．．．
X
1
290
．
．
．
．
．
．
．
．
277
．．．．．．．
276
(4558,-410)
z VOUT maximum -13V (+10% Range)
z ST7565S Temperature gradient = -0.05%/°C
z Logic power supply VDD – VSS = 1.8V to 3.3 V (+10% Range)
z Add new booster ratio 5 times and 6 times
z Use select pin to define display duty as following table
SEL 3 , 2 , 1
0,0,0
DUTY
1/65
BIAS
1/9 or 1/7
0,0,1
1/49
1/8 or 1/6
0,1,0
1/33
1/6 or 1/5
0,1,1
1/55
1/8 or 1/6
1,0,0
1/53
1/8 or 1/6
1, X , X
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Ver 0.3c
2/73
15um 15um
24um
15um
15um
38um
38um
30um
2002/07/22
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