TC9329FA Просмотр технического описания (PDF) - Toshiba
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TC9329FA Datasheet PDF : 83 Pages
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TC9329FA/FB
6. G-Register (G-REG)
The G-register is a 4 bits register used for addressing the low addresses (DR = 4H to FH addresses) of the
data memory’s 192 words.
The contents of this register are validated when the MVGD instruction or MVGS instruction are
executed, and not affected through the execution of any other instructions. This register is used as one of
the ports, and the contents are set when the OUT1 instruction from among the I/O instructions is executed.
The 6-bit contents can be directly set by execution of STIG instruction.
(→ Refer to section in Register Ports.)
7. Data Register (DATA REG)
The data register consists of 1 × 16 bits and loads 16 bits of optional address data. This register is used
as one of the ports, and the contents are loaded into the data memory in units of 4 bits when IN1
instruction from among the I/O instruction is executed. (→ Refer to section #1 in Register Ports.)
Moreover, this register is also possible to writing from data memory and uses it for evacuation/return
processing of the data at the time of interruption.
8. DAL Address Register (DA)
The data register consists of 1 × 14 bits.
If DAL instruction is executed when the DAL bit is set to “1”, 16 bits of the data of the free addresses in
the program memory specified by this DAL address register are loaded. By the setting (DATA) → DA bit to
“1”, the contents of data register (DATA REG) can be transmitted to DAL address register (DA).
This register and a control bit are treated as a port, and are accessed by IN3/OUT3 instruction of an
input-and-output instruction. (→ Refer to register port item)
9. Carry F/F (Ca Flag)
This is set when either Carry or Borrow are issued in the result of calculation instruction execution and
is reset if neither of these are issued.
The contents of carry F/F can only be amended through the execution addition, subtraction, CLT, CLTC
instructions and not affected by the execution of any other instruction.
The carry F/F can be accessed by IN1/OUT1 instruction of an input-and-output instruction. For this
reason, an input-and-output command performs the evacuation and the return at the time of interruption
between data memories. (Refer to register port item)
10. Judgment Circuit (J)
This circuit judges the skip conditions when an instruction equipped with the skip function is executed.
The program counter is increased in increments of two when the skip conditions are satisfied, and the
subsequent instruction is skipped.
There are 15instructions equipped with a wide variety of skip functions available. (→ Refer to the items
marked with a “*” symbol in the Table Instruction Functions and Operational Instructions)
11. Interruption Circuit
An interruption circuit branches to each vector address by the demand from circumference hardware,
and performs each interruption processing. (→ Refer to interruption functional item)
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2002-02-07
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