TC9329FA/FB
I/O Map (IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C))
I/O
φL1
φL2
φL3
φK1
φK2
φK3
OUT1
OUT2
OUT3
IN1
IN2
IN3
Code
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Power control
0
HF
FM
I/O port 1 pull-down
I/O port 1
IF monitor
0
A/D data
I/O port 1
PW0
PW1
PD0
K1
PD2
PD3
-0
-1
-2
-3
BUSY
MANUAL
OVER
AD0
AD1
AD2
AD3
-0
-1
-2
-3
Programmable counter 1
A/D control
I/O port 2
IF data 1
A/D data
I/O port 2
1
P0
P1
P2
P16
AD SEL0 AD SEL1 AD SEL2
STA
-0
-1
-2
-3
F0
F1
F2
F3
AD4
AD5
BUSY
0
-0
-1
-2
-3
Programmable counter 2
Serial interface control 1
I/O port 3
IF data 2
2
P4
P5
P6
P7
edge SCK - INV SCK - I/O SIO-ON
-0
-1
-2
-3
F4
F5
F6
F7
I/O port 3
-0
-1
-2
-3
Programmable counter 3
Serial interface control 2
I/O port 4
IF data 3
Serial interface monitor
I/O port 4
3
0
P8
P9
P10
P11
STA
SO - I/O 8/4 bit SIO Select
-0
-1
-2
-3
F8
F9
F10
F11
BUSY
COUNT
SIO F/F
-0
-1
-2
-3
Programmable counter 4
Serial interface output data 1
I/O port 5
IF data 4
Serial interface input data 1
I/O port 5
4
P12
P13
P14
P15
SO0
SO1
SO2
SO3
-0
-1
-2
-3
F12
F13
F14
F15
SI0
SI1
SI2
SI3
-0
-1
-2
-3
5
Reference select
Programmable
counter
Serial interface output data 2
R0
R1
R2
P16
SO4
SO5
SO6
SO7
IF data 5
Serial interface input data 2
F16
F17
F18
F19
SI4
SI5
SI6
SI7
IF counter control 1
6
Timer reset
CKSTP
Test
port 2
IF1/ 2
PW
IF1/INTR1 IF2/IN2 2 Hz F/F
Clock
mode
#4
Timer
2 Hz F/F
10 Hz
100 Hz
0
IF counter control 2
7
STA/STP MANIAL
G0
Interrupt control
G1
POL1
(INTR1)
POL2
(INTR2)
IE
*
I/O port 8
HOLD
INTR1
INTR2
Interrupt
0
master flag
0
-0
-1
-2
-3
IMF
0
0
I/O port 8
-0
-1
-2
-3
MUTE control
Interrupt permission flag
I/O port 9
MUTE control
Interrupt permission flag
I/O port 9
8
MUTE
I/O-1
POL
HOLD
EF1
(INTR1)
FE2
(INTR2)
FE3
(SIO)
FE4
(Timer)
-0
-1
-2
MUTE
-3
I/O
POL
HOLD
EF1
EF2
EF3
EF4
-0
-1
-2
-3
9
UNLOCK
Detection
RESET
DO2 control
PN
M0
M1
ILR1
(INTR1)
Interrupt latch reset
ILR2
(INTR2)
ILR3
(SIO)
ILR4
(Timer)
HOLD PLL IF counter
off control
Split
Prescaller
IN
PSC ENA
Unlock detection
F/F
ENA
Input port
(INTR1)
IN2
IL1
Interrupt latch
IL2
IL3
IL4
A
BUZZR output control 1
BF0
BF1
BF2
BEN
Timer counter Interrupt detection data1
ID0
ID1
ID2
ID3
DAL
(DATA)
→ DA
OT Count
Up
port 1
Pull-up
Timer counter data 1
DAL
0
0
0
CT0
CT1
CT2
CT3
BUZZR output control 2
Timer counter Interrupt detection data2
DAL address
B
BM0
BM1
BUZR ON
POL
ID4
ID5
ID6
ID7
DA0
DA1
DA2
DA3
Timer counter data 2
DAL address
CT4
CT5
CT6
CT7
DA0
DA1
DA2
DA3
Timer counter control
Data register 1
C
CA Flag
*
*
*
CA flag
0
0
0
CK0
CK1
GT
CR
d0
d1
d2
d3
Data register 1
d0
d1
d2
d3
G register 1
Data select
Data register 2
G register 1
Data select
Data register 2
D
G0
G1
G2
G3
SEL1
SEL2
SEL4
SEL8
d4
d5
d6
d7
G0
G1
G2
G3
S1
S2
S3
S4
d4
d5
d6
d7
G register 2
Segment data 1/ General purpose output data
Data register 3
G register 2
E
G4
G5
*
*
COM1/OT COM2/OT COM3/OT COM4/OT
d8
d9
d10
d11
G4
G5
0
0
Data register 3
d8
d9
d10
d11
Test port 1
Segment data2/ Segment IO control
Data register 4
F
#0
#1
#2
#3
COM1
COM2
COM3
COM4
d12
d13
d14
d15
Data register 4
d12
d13
d14
d15
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21
2002-02-07