CY8C26443-24PI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C26443-24PI Datasheet PDF : 148 Pages
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Table 4: Pin-out 28 Pin
Name I/O
P0[7] I/O
P0[5] I/O
P0[3] I/O
P0[1] I/O
P2[7] I/O
P2[5] I/O
P2[3] I/O
P2[1] I/O
SMP
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I
P2[0] I/O
P2[2] I/O
P2[4] I/O
P2[6] I/O
P0[0] I/O
P0[2] I/O
P0[4]
P0[6]
Vcc
I/O
I/O
Power
Pin
Description
1 Port 0[7] (Analog Input)
2
Port 0[5] (Analog Input/ Out-
put)
3
Port 0[3] (Analog Input/ Out-
put)
4 Port 0[1] (Analog Input)
5 Port 2[7]
6 Port 2[5]
7
Port 2[3] (Non-Multiplexed
Analog Input)
8
Port 2[1] (Non-Multiplexed
Analog Input)
9 Switch Mode Pump
10 Port 1[7]
11 Port 1[5]
12 Port 1[3]
13 Port 1[1] / XtalIn / SCLK
14 Ground
15 Port 1[0] / XtalOut / SDATA
16 Port 1[2]
17 Port 1[4]
18 Port 1[6]
19 External Reset
20
Port 2[0] (Non-Multiplexed
Analog Input)
21
Port 2[2] (Non-Multiplexed
Analog Input)
22 Port 2[4] / External AGNDIn
23 Port 2[6] / External VREFIn
24 Port 0[0] (Analog Input)
25
Port 0[2] (Analog Input/Out-
put)
26
Port 0[4] (Analog Input/Out-
put)
27 Port 0[6] (Analog Input)
28 Supply Voltage
P0[7]
1
P0[5]
2
P0[3]
3
P0[1]
4
P2[7]
5
P2[5]
6
P2[3]
7
P2[1]
8
SMP
9
P1[7]
10
P1[5]
11
P1[3]
12
XtalIn/SCLK/P1[1]
13
Vss
14
28
27
Vcc
P0[6]
26
P0[4]
25
P0[2]
24
P0[0]
23
22
21
20
19
18
17
16
15
P2[6]/External Vref
P2[4]/External AGND
P2[2]
P2[0]
Xres
P1[6]
P1[4]
P1[2]
P1[0]/XtalOut/SDATA
Figure 4: 26443 PDIP/SOIC/SSOP
Table 5: Pin-out 44 Pin
Name I/O
P2[5] I/O
P2[3] I/O
P2[1]
P3[7]
P3[5]
P3[3]
P3[1]
SMP
P4[7]
P4[5]
P4[3]
P4[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
P4[0]
P4[2]
P4[4]
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin
Description
1 Port 2[5]
2
Port 2[3] (Non-Multiplexed
Analog Input)
3
Port 2[1] (Non-Multiplexed
Analog Input)
4 Port 3[7]
5 Port 3[5]
6 Port 3[3]
7 Port 3[1]
8 Switch Mode Pump
9 Port 4[7]
10 Port 4[5]
11 Port 4[3]
12 Port 4[1]
13 Port 1[7]
14 Port 1[5]
15 Port 1[3]
16 Port 1[1] / XtalIn / SCLK
17 Ground
18 Port 1[0] / XtalOut / SDATA
19 Port 1[2]
20 Port 1[4]
21 Port 1[6]
22 Port 4[0]
23 Port 4[2]
24 Port 4[4]
16
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
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