ST8024LC Просмотр технического описания (PDF) - STMicroelectronics
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ST8024LC Datasheet PDF : 35 Pages
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ST8024L
Electrical characteristics
Table 15. Clock output to card reader (pin CLK)
Symbol
Parameter(1)
Test conditions
Min. Typ.
VO(inactive)
Output voltage in inactive
mode
IO(inactive) = 1 mA
No load
0
-
0
-
IO(inactive) Output current
CLK inactive mode;
pin grounded
0
-
VOL
VOH
tR, tF
δ
SR
Low level output voltage
IOL = 200 µA
IOL = 70 mA (current limit)
High level output voltage
Rise and fall time
Duty factor (except for fXTAL)
IOH = –200 µA
IOH = –70 mA (current limit)
CL = 30 pF(2)
CL = 30 pF(2)
Slew rate
Slew up or down; CL = 30 pF
0
-
VCC -0.4
-
0.9 VCC
-
0
-
-
45
-
0.2
-
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
2. Transition time and duty factor definitions are shown in Figure 3; d = t1/(t1+ t2).
Max.
0.3
0.1
–1
0.3
VCC
VCC
0.4
16
55
Unit
V
mA
V
V
ns
%
V/ns
Table 16. Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V and PORADJ/1.8V)
Symbol
Parameter(1)
Test conditions
Min. Typ. Max. Unit
VIL
Low level input voltage
VIH
High level input voltage
|ILIH|
High level input leakage
current
VIH = VDD
VIH = VDD, 1.8V and CLKDIV2
pins with internal 11 kΩ pull-
down resistor
–0.3
0.7 VDD
0.3 VDD V
VDD
V
1
µA
800
µA
VIL = 0
-1
µA
|ILIL|
Low level input leakage
current
VIL = 0, CLKDIV1 pin with
internal 11 kΩ pull-up resistor
-800
µA
RPD
Internal pull-down resistor to Pull-down resistor to GND (1.8V
GND
and CLKDIV2 pins)
9
11
13
kΩ
RPU
Internal pull-up resistor to
VDD
Pull-up resistor to VDD
(CLKDIV1 pin)
9
11
13
kΩ
1. VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
Pin CMDVCC is active low; pin RSTIN is active high; for CLKDIV1 and CLKDIV2 functions (see Table 21).
Doc ID 17709 Rev 5
15/35
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