73K222AL-IGT Просмотр технического описания (PDF) - TDK Corporation
Номер в каталоге
Компоненты Описание
производитель
73K222AL-IGT Datasheet PDF : 28 Pages
| |||
73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETER
CONDITION
MIN
Guard Tone Generator
Tone Accuracy
550 Hz
1800 Hz
-20
Tone Level
550 Hz
-4.0
(Below DPSK Output)
1800 Hz
-7.0
Harmonic Distortion
700 to 2900 Hz
550 Hz
1800 Hz
Timing (Refer to Timing Diagrams)
TAL
CS/Address setup before ALE Low 12
TLA
CS CS hold after ALE low
0
TLC
TCL
TRD
ADDR Address hold after ALE low
10
ALE Low to RD/WR Low
10
RD/ WR Control to ALE High
0
Data out from RD Low
0
TLL
TRDF
TRW
TWW
TDW
TWD
ALE width
15
Data float after RD High
RD width
50
WR width
50
Data setup before WR High
15
Data hold after WR High
12
TCKD
TCKW
Data out after EXCLK Low
WR after EXCLK Low
150
TDCK
Data setup before EXCLK Low
150
TAC
Address setup before control*
50
TCA
Address hold after control*
50
TWH
Data Hold after EXCLK
20
NOM
-3.0
-6.0
MAX
+20
-2.0
-5.0
-50
-60
140
50
200
UNIT
Hz
dB
dB
dB
dB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
19
Share Link: 