DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

DS18S20-PAR Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

Номер в каталоге
Компоненты Описание
производитель
DS18S20-PAR
Dallas
Dallas Semiconductor -> Maxim Integrated 
DS18S20-PAR Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
DS18S20-PAR
DETAILED PIN DESCRIPTIONS Table 1
PIN SYMBOL
DESCRIPTION
1
GND Ground.
2
DQ Data Input/Output pin. Open-drain 1-wire interface pin. Also provides power
to the device when used in parasite power mode (see “Parasite Power” section.)
3
NC
No Connect. Doesn’t connect to internal circuit.
OVERVIEW
The DS18S20-PAR uses Dallas’ exclusive 1-wire bus protocol that implements bus communication using
one control signal. The control line requires a weak pullup resistor since all devices are linked to the bus
via a 3-state or open-drain port (the DQ pin in the case of the DS18S20-PAR). In this bus system, the
microprocessor (the master device) identifies and addresses devices on the bus using each device’s
unique 64-bit code. Because each device has a unique code, the number of devices that can be addressed
on one bus is virtually unlimited. The 1-wire bus protocol, including detailed explanations of the
commands and “time slots,” is covered in the 1-WIRE BUS SYSTEM section of this datasheet.
An important feature of the DS18S20-PAR is its ability to operate without an external power supply.
Power is instead supplied through the 1-wire pullup resistor via the DQ pin when the bus is high. The
high bus signal also charges an internal capacitor (CPP), which then supplies power to the device when the
bus is low. This method of deriving power from the 1-wire bus is referred to as “parasite power.”
Figure 1 shows a block diagram of the DS18S20-PAR, and pin descriptions are given in Table 1. The
64-bit ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte
temperature register that stores the digital output from the temperature sensor. In addition, the scratchpad
provides access to the 1-byte upper and lower alarm trigger registers (TH and TL). The TH and TL
registers are nonvolatile (EEPROM), so they will retain their data when the device is powered down.
DS18S20-PAR BLOCK DIAGRAM Figure 1
VPU
4.7K
DQ
PARASITE POWER
CIRCUIT
INTERNAL VDD
CPP
64-BIT ROM
AND
1-wire PORT
GND
MEMORY CONTROL DS18S20-PAR
LOGIC
SCRATCHPAD
TEMPERATURE SENSOR
ALARM HIGH TRIGGER (TH)
REGISTER (EEPROM)
ALARM LOW TRIGGER (TL)
REGISTER (EEPROM)
8-BIT CRC GENERATOR
2 of 20

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]