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LT1767-5

Monolithic 1.5A, 1.25MHz Step-Down Switching Regulators

Linear Technology 

LT1767/LT1767-1.8/

LT1767-2.5/LT1767-3.3/LT1767-5

APPLICATIONS INFORMATION

Example: switching should not start until the input is

above 4.75V and is to stop if the input falls below 3.75V.

VH = 4.75V

VL = 3.75V

R1= 4.75V − 3.75V =143k

7µA

R2

=

(4.75V

1.33V

− 1.33V)

+

3µA

=

49.4k

143k

Keep the connections from the resistors to the SHDN

pin short and make sure that the interplane or surface

capacitance to the switching nodes are minimized. If high

resistor values are used, the SHDN pin should be bypassed

with a 1nF capacitor to prevent coupling problems from

the switch node.

SYNCHRONIZATION

The SYNC pin, is used to synchronize the internal oscillator

to an external signal. The SYNC input must pass from a

logic level low, through the maximum synchronization

threshold with a duty cycle between 20% and 80%. The

input can be driven directly from a logic level output. The

synchronizing range is equal to initial operating frequency

up to 2MHz. This means that minimum practical sync

frequency is equal to the worst-case high self-oscillating

frequency (1.5MHz), not the typical operating frequency

of 1.25MHz. Caution should be used when synchronizing

above 1.6MHz because at higher sync frequencies the

amplitude of the internal slope compensation used to

prevent subharmonic switching is reduced. This type of

subharmonic switching only occurs at input voltages less

than twice output voltage. Higher inductor values will tend

to eliminate this problem. See Frequency Compensation

section for a discussion of an entirely different cause of

subharmonic switching before assuming that the cause

is insufficient slope compensation. Application Note 19

has more details on the theory of slope compensation.

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maxi-

mum efficiency, switch rise and fall times are typically

in the nanosecond range. To prevent noise both radiated

and conducted, the high speed switching current path,

shown in Figure 5, must be kept as short as possible.

This is implemented in the suggested layout of Figure 6.

Shortening this path will also reduce the parasitic trace

inductance of approximately 25nH/inch. At switch-off, this

parasitic inductance produces a flyback spike across the

LT1767 switch. When operating at higher currents and

input voltages, with poor layout, this spike can generate

voltages across the LT1767 that may exceed its absolute

maximum rating. A ground plane should always be used

under the switcher circuitry to prevent interplane coupling

and overall noise.

LT1767

VIN

SW

L1

5V

VIN C3

HIGH

FREQUENCY

CIRCULATING

PATH

D1 C1

LOAD

1767 F05

Figure 5. High Speed Switching Path

The VC and FB components should be kept as far away as

possible from the switch and boost nodes. The LT1767

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability

or subharmonic like oscillation.

Board layout also has a significant effect on thermal re-

sistance. Soldering the exposed pad to as large a copper

area as possible and placing feedthroughs under the pad

to a ground plane, will reduce die temperature and increase

the power capacity of the LT1767. For the nonexposed

package, Pin 4 is connected directly to the pad inside the

package. Similar treatment of this pin will result in lower

die temperatures.

12

For more information www.linear.com/LT1767

1767fb

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