LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
VIN
12V C3
2.2µF
CERAMIC
D2
CMDSH-3
OPEN
OR
HIGH
= ON
C2
0.1µF
BOOST
VIN
VSW
LT1767-2.5
SHDN
FB
SYNC GND VC
CC
1.5nF
RC
4.7k
L1
5µH
D1
UPS120
OUTPUT
2.5V
1.2A
C1
10µF
CERAMIC
1767 F06a
C3
VIN
MINIMIZE LT1767,
C3, D1 LOOP
D2
C2
GND
PLACE FEEDTHROUGHS
AROUND GROUND PIN
AND UNDER GROUND PAD
FOR GOOD THERMAL
CONDUCTIVITY
SYNC
SHDN
KEEP FB AND VC
COMPONENTS
AWAY FROM
HIGH INPUT
COMPONENTS
D1
CC
L1
RC
VOUT
C1 GND
CONNECT TO
GROUND PLANE
KELVIN SENSE
VOUT
1767 F06
Figure 6. Typical Application and Suggested Layout (Topside Only Shown)
THERMAL CALCULATIONS
Power dissipation in the LT1767 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following
formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating efficiency at light
load currents.
Switch loss:
PSW
= RSW
(IOUT )2
VIN
(VOUT )
+ 17ns
(IOUT) (VIN) (f)
Boost current loss for VBOOST = VOUT:
( ) PBOOST
=
VOUT 2
IOUT
VIN
/ 50
Quiescent current loss:
PQ =VIN (0.001)
RSW = Switch resistance (≈ 0.27Ω when hot)
17ns = Equivalent switch current/voltage overlap time
f = Switch frequency
1767fb
For more information www.linear.com/LT1767
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