P87LPC768FN Просмотр технического описания (PDF) - Philips Electronics
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производитель
P87LPC768FN
Philips Electronics
P87LPC768FN Datasheet PDF : 65 Pages
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Philips Semiconductors
Low power, low price, low pin count (20 pin) microcontroller
with 4 kB OTP 8-bit A/D, Pulse Width Modulator
Preliminary data
P87LPC768
Name
KBI#
P0*
P1*
P2*
P0M1#
P0M2#
P1M1#
P1M2#
P2M1#
P2M2#
PCON
PSW*
PT0AD#
Description
Keyboard Interrupt
Port 0
Port 1
Port 2
Port 0 output mode 1
Port 0 output mode 2
Port 1 output mode 1
Port 1 output mode 2
Port 2 output mode 1
Port 2 output mode 2
Power control register
Program status word
Port 0 digital input disable
SFR
Address
86h
80h
90h
A0h
84h
85h
91h
92h
A4h
A5h
87h
D0h
F6h
MSB
87
T1
97
(P1.7)
A7
–
(P0M1.7)
(P0M2.7)
(P1M1.7)
(P1M2.7)
P2S
–
SMOD1
D7
CY
86
CMP1
96
(P1.6)
A6
–
(P0M1.6)
(P0M2.6)
(P1M1.6)
(P1M2.6)
P1S
–
SMOD0
D6
AC
Bit Functions and Addresses
85
84
83
82
CMPREF CIN1A CIN1B CIN2A
95
94
93
92
RST INT1 INT0
T0
A5
A4
A3
A2
–
–
–
–
(P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2)
(P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2)
–
(P1M1.4)
–
–
–
(P1M2.4)
–
–
P0S ENCLK T1OE T0OE
–
–
–
–
BOF POF GF1 GF0
D5
D4
D3
D2
F0
RS1 RS0
OV
81
CIN2B
91
RxD
A1
X1
(P0M1.1)
(P0M2.1)
(P1M1.1)
(P1M2.1)
(P2M1.1)
(P2M2.1)
PD
D1
F1
LSB
80
CMP2
90
TxD
A0
X2
(P0M1.0)
(P0M2.0)
(P1M1.0)
(P1M2.0)
(P2M1.0)
(P2M2.0)
IDL
D0
P
Reset
Value
00h
Note 2
Note 2
Note 2
00h
00H
00h1
00h1
00h
00h1
Note 3
00h
00h
9F
9E
9D
9C
9B
9A
99
98
PWMCON0 PWM Control Register 0
DAh RUN XFER PWM3I PWM2I –
PWM1I PWM0I –
00h
PWMCON1 PWM Control Register 1
DBh BKCH BKPS BPEN BKEN PWM3B PWM2B PWM1B PWM0B 00h
SCON* Serial port control
98h
SM0
SM1
SM2
REN
TB8
RB8
TI
RI 00h
SBUF
Serial port data buffer
register
99h
xxh
SADDR# Serial port address register A9h
00h
SADEN# Serial port address enable B9h
00h
SP
Stack pointer
81h
07h
TCON*
TH0
TH1
TL0
TL1
TMOD
Timer 0 and 1 control
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
Timer 0 and 1 mode
8F
8E
8D
8C
8B
8A
89
88
88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0 00h
8Ch
00h
8Dh
00h
8Ah
00h
8Bh
00h
89h GATE C/T
M1
M0 GATE C/T
M1
M0 00h
WDCON# Watchdog control register
A7h
–
–
WDOVF WDRUN WDCLK WDS2 WDS1 WDS0 Note 4
WDRST# Watchdog reset register
A6h
xxh
NOTES:
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset value shown in the table for these bits is 0.
2. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte.
3. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon
power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up.
4. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00
0000b for all other reset causes if the watchdog is disabled.
2002 Mar 12
8
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