7C4261V-10(2003) Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

7C4261V-10
(Rev.:2003)

16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Programmable Almost Full Flag Timing

tCLKH

tCLKL

WCLK

WEN1

tENS tENH

WEN2

(if applicable)

PAF

tENS tENH

FULL − (M+1)WORDS

IN FIFO

RCLK

REN1,

REN2

Note 22

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Note 23

tPAF

(FULL −M) WORDS

IN FIFO [24]

tSKEW2 [25]

tENS

tENS tENH

tPAF

Write Programmable Registers

tCLKH

tCLK

tCLKL

WCLK

WEN2/LD

tENS

tENH

WEN1

tENS

tDS

tDH

D0 –D8

PAE OFFSET

LSB

PAE OFFSET

MSB

PAF OFFSET

LSB

PAF OFFSET

MSB

Notes:

22. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.

23. PAF offset = m.

24. 16K − m words for CY7C4261V, 32K – m words for CY7C4271V, 64K − m words for CY7C4281V, and 128K − m words for CY4291V.

25. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK

and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.

Document #: 38-06013 Rev. *A

Page 13 of 16

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