74LCX32500 Просмотр технического описания (PDF) - Fairchild Semiconductor

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74LCX32500

Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs

Fairchild Semiconductor 

Connection Diagram

(Top Thru View)

Truth Table (Note 4)

Inputs

Output

OEABn LEABn CLKABn An

Bn

L

X

X

X

Z

H

H

X

L

L

H

H

X

H

H

H

L

↓

L

L

H

L

↓

H

H

H

L

H

X

H

L

L

X

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial (HIGH or LOW, inputs may not float)

Z = High Impedance

B0 (Note 5)

B0 (Note 6)

Note 4: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,

LEBA, and CLKBA.

Note 5: Output level before the indicated steady-state input conditions

were established.

Note 6: Output level before the indicated steady-state input conditions

were established, provided that CLKAB was LOW before LEAB went LOW.

Pin Descriptions

Pin Names

Description

1A1 - 1A18

2A1 - 2A18

1B1 - 1B18

2B1 - 2B18

Data Register A Inputs/3-STATE Outputs

Data Register B Inputs/3-STATE Outputs

CLKAB1, CLKBA1 Clock Pulse Inputs

CLKAB2, CLKBA2

LEAB1, LEBA1 Latch Enable Inputs

LEAB2, LEBA2

OEAB1, OEBA1

OEAB2, OEBA2

Output Enable Inputs

FBGA Pin Assignments

1

2

3

4

5

6

A

1A2 1A1 LEAB1 CLKAB1 1B1

1B2

B

1A4 1A3 OEAB1 GND

1B3

1B4

C

1A6 1A5 GND GND

1B5

1B6

D

1A8 1A7 VCC

VCC

1B7

1B8

E 1A10 1A9 GND GND

1B9 1B10

F

1A12 1A11 GND GND

1B11 1B12

G 1A14 1A13 VCC

VCC

1B13 1B14

H

1A15 1A16 GND GND

1B16 1B15

J

1A17 1A18 OEBA1 CLKBA1 1B18 1B17

K

NC LEAB2 LEBA1 GND CLKAB2 NC

L

2A2 2A1 OEAB2 GND

2B1

2B2

M

2A4 2A3 GND GND

2B3

2B4

N

2A6 2A5 VCC

VCC

2B5

2B6

P

2A8 2A7 GND GND

2B7

2B8

R 2A10 2A9 GND GND

2B9 2B10

T

2A12 2A11 VCC

VCC

2B11 2B12

U

2A14 2A13 GND GND

2B13 2B14

V 2A15 2A16 OEBA2 CLKBA2 2B16 2B15

W 2A17 2A18 LEBA2 GND

2B18 2B17

Functional Description

For A-to-B data flow, the LCX32500 operates in the trans-

parent mode when LEAB is HIGH. When LEAB is LOW,

the A data is latched if CLKAB is held at a HIGH or LOW

logic level. If LEAB is LOW, the A bus data is stored in the

latch/flip-flop on the HIGH-to-LOW transition of CLKAB.

Output-enable OEAB is active-HIGH. When OEAB is

HIGH, the outputs are active. When OEAB is LOW, the out-

puts are in the high impedance state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, and CLKBA. The output enables are com-

plementary (OEAB is active HIGH and OEBA is active

LOW).

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