AD5425_16 Просмотр технического описания (PDF) - Analog Devices

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AD5425_16

8-Bit, High Bandwidth Multiplying DAC with Serial Interface

Analog Devices 

Data Sheet

Bipolar Operation

In some applications, it may be necessary to generate full

4-quadrant multiplying operation or a bipolar output swing.

This can be easily accomplished by using another external

amplifier and some external resistors, as shown in Figure 31. In

this circuit, the second amplifier, A2, provides a gain of 2. Biasing

the external amplifier with an offset from the reference voltage,

results in full 4-quadrant multiplying operation. The transfer

function of this circuit shows that both negative and positive

output voltages are created as the input data, D, is incremented

from code zero (VOUT = −VREF), to midscale (VOUT = 0 V ), to full

scale (VOUT = +VREF).

( ) VOUT = VREF × D / 2n−1 − VREF

Where D is the fractional representation of the digital word

loaded to the DAC and n is the resolution of the DAC.

When VIN is an ac signal, the circuit performs 4-quadrant

multiplication.

Table 6 shows the relationship between digital code and the

expected output voltage for bipolar operation.

Table 6. Bipolar Code Table

Digital Input

Analog Output (V)

1111 1111

+VREF (127/128)

1000 0000

0

0000 0001

−VREF (127/128)

0000 0000

−VREF (128/128)

Stability

In the I to V configuration, the IOUT of the DAC and the

inverting node of the operational amplifier must be connected

as closely as possible and proper printed circuit board (PCB)

layout techniques must be employed. Since every code change

corresponds to a step function, gain peaking can occur if the

operational amplifier has limited gain bandwidth product (GBP)

and there is excessive parasitic capacitance at the inverting node.

This parasitic capacitance introduces a pole into the open-loop

response, which can cause ringing or instability in closed-loop

applications.

An optional compensation capacitor, C1, can be added in parallel

with RFB for stability, as shown in Figure 30 and Figure 31. Too

small a value of C1 can produce ringing at the output, while too

large a value can adversely affect the settling time. C1 must be

found empirically, but 1 pF to 2 pF is generally adequate for

compensation.

SINGLE-SUPPLY APPLICATIONS

Current Mode Operation

In the current mode circuit of Figure 32, IOUT2 and hence IOUT1

is biased positive by an amount applied to VBIAS. In this config-

uration, the output voltage is given by

VOUT = [D × (RFB/RDAC) × (VBIAS − VIN)] + VBIAS

AD5425

As D varies from 0 to 255, the output voltage varies from

VOUT = VBIAS to VOUT = 2VBIAS − VIN

VDD

VDD

RFB

VIN

VREF

IOUT1

IOUT2

GND

C1

AA11

VOUT

VBIAS

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE

REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 32. Single-Supply Current Mode Operation

VBIAS must be a low impedance source capable of sinking and

sourcing all possible variations in current at the IOUT2 terminal

without any problems.

It is important to note that VIN is limited to low voltages because

the switches in the DAC ladder no longer have the same source-

drain drive voltage. As a result, the on resistance differs and this

degrades the linearity of the DAC.

Voltage Switching Mode of Operation

Figure 33 shows this DAC operating in the voltage switching

mode. The reference voltage VIN is applied to the IOUT1 pin, IOUT2 is

connected to AGND, and the output voltage is available at the VREF

terminal. In this configuration, a positive reference voltage results

in a positive output voltage, making single-supply operation

possible. The output from the DAC is voltage at a constant

impedance (the DAC ladder resistance), thus an operational

amplifier is necessary to buffer the output voltage. The

reference input no longer sees constant input impedance, but

one that varies with code. So, the voltage input must be driven

from a low impedance source.

VDD

R1

R2

RFB

VDD

VIN

IOUT1

IOUT2

VREF

GND

AA11

VOUT

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 33. Single-Supply Voltage Switching Mode Operation

Rev. D | Page 15 of 24

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