74LV165N Просмотр технического описания (PDF) - NXP Semiconductors.
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74LV165N Datasheet PDF : 14 Pages
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Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
74LV165
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V.
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
D7 INPUT
VM
GND
VOH
Q7 OUTPUT
VOL
tPLH
tPHL
VM
VOH
Q7 OUTPUT
VOL
tPHL
tPLH
VM
SV00592
Figure 3. Data input (Dn) to output (Q7 or Q7) propagation
delays when PL is LOW.
VI
CP, CE
INPUT
GND
VI
DS INPUT
see note
VM
tsu (L)
th
stable
VM
th
tsu (H)
GND
tsu
th
tW
VI
CP, CE
INPUT
VM
GND
CE may change only from HIGH-to-LOW while CP is LOW. The shaded
areas indicate when the input is permitted to change for predictable output
performance.
SV00595
Figure 4. Set-up and hold times from the serial data input (DS) to
the clock (CP) and the clock enable (CE) inputs, from the clock
enable input (CE) to the clock input (CP) and from the clock input
(CP) to the clock enable input (CE).
Note to Figure 4
CE may change only from HIGH-to-LOW while CP is LOW. The
shaded areas indicate when the input is permitted to change for
predictable output performance.
VI
Dn INPUT
GND
VI
VM
tsu
tH
tsu
tH
PL INPUT
VM
GND
SV00593
Figure 5. Set-up and hold times from the data inputs (Dn)
to the parallel load input (PL).
TEST CIRCUIT
Vcc
PULSE
GENERATOR
Vl
RT
D.U.T.
VO
50pF
CL
RL= 1k
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST
tPLH/tPHL
VCC
< 2.7V
2.7–3.6V
≥ 4.5 V
VI
VCC
2.7V
VCC
SV00902
Figure 6. Load circuitry for switching times.
1998 May 07
8
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