IDT7026L20GG(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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Компоненты Описание

производитель

IDT7026L20GG
(Rev.:2015)

HIGH-SPEED 16K X 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

HIGH-SPEED

16K X 16 DUAL-PORT

STATIC RAM

IDT7026S/L

Features

◆ True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆ High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

– Military: 20/25/35/55ns (max.)

◆ Low-power operation

– IDT7026S

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7026L

Active: 750mW (typ.)

Standby: 1mW (typ.)

◆ Separate upper-byte and lower-byte control for multi-

plexed bus compatibility

Functional Block Diagram

R/WL

UBL

◆ IDT7026 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆ M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

◆ On-chip port arbitration logic

◆ Full on-chip hardware support of semaphore signaling

between ports

◆ Fully asynchronous operation from either port

◆ TTL-compatible, single 5V (±10%) power supply

◆ Available in 84-pin PGA and 84-pin PLCC

◆ Industrial temperature range (-40°C to +85°C) is available

for selected speeds

◆ Green parts available, see ordering information

R/WR

UBR

LBL

LBR

CEL

CER

OEL

OER

I/O8L-I/O15L

I/O0L-I/O7L

BUSYL(1,2)

A13L

A0L

I/O

Control

I/O

Control

Address

Decoder

14

CEL

MEMORY

ARRAY

ARBITRATION

SEMAPHORE

LOGIC

Address

Decoder

14

CER

SEML

M/S

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs are non-tri-stated push-pull.

1

©2015 Integrated Device Technology, Inc.

I/O8R-I/O15R

I/O0R-I/O7R

BUSYR(1,2)

A13R

A0R

SEMR

2939 drw 01

AUGUST 2015

DSC 2939/14

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