74ALVT16373 Просмотр технического описания (PDF) - NXP Semiconductors.
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74ALVT16373 Datasheet PDF : 16 Pages
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Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
10.1 Waveforms and test circuit
VI
nDn input
VM
VM
GND
VOH
tPHL
tPLH
nQn output
VM
VM
VOL
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Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with
the output load.
Figure 5. Input (nDn) to output (nQn) propagation delays
VI
nOE input
VM
VI
nLE input
GND
VOH
nQn output
VOL
VM
VM
tW
tPHL
VM
VM
tPLH
VM
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Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur
with the output load.
Figure 6. Latch enable input (nLE) to data output (nQn)
propagation delays and pulse width
VM
GND
3.0 V or VCC
output
LOW-to-OFF
OFF-to-LOW
VOL
tPLZ
VX
tPHZ
tPZL
VM
tPZH
VOH
output
HIGH-to-OFF
OFF-to-HIGH
GND
VY
outputs
enabled
outputs
disabled
VM
outputs
enabled
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Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 7. OFF-state to HIGH or LOW and HIGH or LOW to OFF-state propagation delays
VI
nDn input
VM
GND
VI
th
tsu
th
tsu
nLE input
VM
GND
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 8. Input (nDn) to input (nLE) data set-up and hold times
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74ALVT16373
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 2 February 2018
© Nexperia B.V. 2018. All rights reserved.
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