74LVC00ADB,112 Просмотр технического описания (PDF) - NXP Semiconductors.

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74LVC00ADB,112

Quad 2-input NAND gate

NXP Semiconductors. 

74LVC00A

Quad 2-input NAND gate

Rev. 7 — 25 April 2012

Product data sheet

1. General description

The 74LVC00A provides four 2-input NAND gates.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V applications.

2. Features and benefits

 5 V tolerant inputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low-power consumption

 Direct interface with TTL levels

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from −40 °C to +85 °C and −40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range

74LVC00AD −40 °C to +125 °C

74LVC00ADB −40 °C to +125 °C

74LVC00APW −40 °C to +125 °C

74LVC00ABQ −40 °C to +125 °C

Name

Description

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SSOP14

plastic shrink small outline package; 14 leads;

body width 5.3 mm

TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

Version

SOT108-1

SOT337-1

SOT402-1

SOT762-1

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