MK10FX256ZVLL10 Просмотр технического описания (PDF) - NXP Semiconductors.
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MK10FX256ZVLL10 Datasheet PDF : 75 Pages
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Peripheral operating requirements and behaviors
Table 44. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage
range) (continued)
Num.
Characteristic
Min.
Max.
Unit
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
0
I2S_RX_FS output invalid
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S1
S2
S2
S3
S4
S4
S5
S9
S7
S9
S10
S7
S8
S6
S10
S8
Figure 25. I2S/SAI timing — master modes
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num.
S11
S12
S13
S14
S15
Characteristic
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
• Multiple SAI Synchronous mode
• All other modes
Min.
2.7
80
45%
4.5
2
—
—
Max.
3.6
—
55%
—
—
21
15
Unit
V
ns
MCLK period
ns
ns
ns
Table continues on the next page...
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc.
59
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