NCP1612B Просмотр технического описания (PDF) - ON Semiconductor

Номер в каталоге

Компоненты Описание

производитель

NCP1612B

Enhanced, High‐Efficiency Power Factor Controller

ON Semiconductor 

NCP1612A, NCP1612B, NCP1612A1, NCP1612A2, NCP1612A3, NCP1612B2

Table 4. DETAILED PIN DESCRIPTION

Pin Number

Name

Function

1

FOVP

Vpin1 is the input signal for the Fast Over-voltage (FOVP). The circuit disables the driver if

Vpin1 exceeds the FOVP threshold which is set 2% higher than the reference for the soft OVP

comparator (that monitors the feedback pin) so that pins 1 and 2 can receive the same portion

of the output voltage.

With the NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B, Vpin1 is also used for

under-voltage detection (UVP2) and Bulk Under Voltage (BUV) detection. The BUV

comparator disables the driver and grounds the pfcOK pin when Vpin1 drops below 76% of the

2.5 V reference voltage in the A and B versions and below 40% of the 2.5 V reference voltage

in the A1/A3 version. The BUV function has no action whenever the pfcOK pin is in low state.

A 250 nA sink current is built-in to ground the pin if the pin is accidentally open.

2

Feedback

This pin receives a portion of the PFC output voltage for the regulation and the Dynamic

Response Enhancer (DRE) that drastically speeds-up the loop response when the output

voltage drops below 95.5% of the desired output level.

Vpin2 is also the input signal for the Over-voltage (OVP) and Under-voltage (UVP)

comparators. The UVP comparator prevents operation as long as Vpin2 is lower than 12% of

the reference voltage (VREF). A soft OVP comparator gradually reduces the duty-ratio to zero

when Vpin2 exceeds 105% of VREF (soft OVP). With the NCP1612A2 and the NCP1612B2,

Vpin2 is used for Bulk Under Voltage (BUV) detection.

A 250 nA sink current is built-in to trigger the UVP protection and disable the part if the

feedback pin is accidentally open.

3

VCONTROL

The error amplifier output is available on this pin. The network connected between this pin and

ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high

Power Factor ratios.

Pin3 is grounded when the circuit is off so that when it starts operation, VCONTROL slowly

charges up to provide a soft-start function with the A, A1, A2 and A3 versions which disables

the dynamic response enhancer (DRE) until the startup phase is completed. With the versions

optimized for self-powered PFC stages (NCP1612B and NCP1612B2), DRE speeds-up the

VCONTROL charge for a shortened startup phase.

4

VSENSE

A portion of the instantaneous input voltage is to be applied to pin4 in order to detect brown-out

conditions. If Vpin4 is lower than 0.9 V for more than 50 ms, the circuit stops pulsing until the pin

voltage rises again and exceeds 1 V.

This pin also detects the line range. By default, the circuit operates the “low-line gain” mode.

If Vpin4 exceeds 2.2 V, the circuit detects a high-line condition and reduces the loop gain by 3.

Conversely, if the pin voltage remains lower than 1.7 V for more than 25 ms, the low-line gain is

set.

Connecting the pin 4 to ground disables the part once the 50-ms blanking time has elapsed.

5

FFCONTROL

This pin sources a current representative to the line current. Connect a resistor between pin5

and ground to generate a voltage representative of the line current. When this voltage exceeds

the internal 2.5 V reference (VREF), the circuit operates in critical conduction mode. If the pin

voltage is below 2.5 V, a dead-time is generated that approximately equates

[66 ms • (1 − (Vpin5/VREF))]. By this means, the circuit forces a longer dead-time when the

current is small and a shorter one as the current increases.

The circuit skips cycles whenever Vpin5 is below 0.65 V to prevent the PFC stage from

operating near the line zero crossing where the power transfer is particularly inefficient. This

does result in a slightly increased distortion of the current. If superior power factor is required,

offset pin 5 by more than 0.75 V offset to inhibit the skip function.

6

CS/ZCD

This pin monitors the MOSFET current to limit its maximum current.

This pin is also connected to an internal comparator for Zero Current Detection (ZCD). This

comparator is designed to monitor a signal from an auxiliary winding and to detect the core

reset when this voltage drops to zero. The auxiliary winding voltage is to be applied through a

diode to avoid altering the current sense information for the on-time (see application schematic).

7

Ground

Connect this pin to the PFC stage ground.

8

Drive

The high-current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to

effectively drive high gate charge power MOSFETs.

9

VCC

This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 10.5 V

(A, A1, A2 and A3 versions, 17.0 V for the B and B2 versions) and turns off when VCC goes

below 9.0 V (typical values). After start-up, the operating range is 9.5 V up to 35 V. The A, A1,

A2 and A3 versions are preferred in applications where the circuit is fed by an external power

source (from an auxiliary power supply or the downstream converter). Its maximum start-up

level (11.25 V) is set low enough so that the circuit can be powered from a 12 V rail. The B and

B2 versions are optimized for applications where the PFC stage is self-powered.

10

pfcOK

This pin is grounded until the PFC output has reached its nominal level. It is also grounded if

the NCP1612 detects a fault. For the rest of the time, i.e., when the PFC stage outputs the

nominal bulk voltage, pin10 is in high-impedance state.

The NCP1612A, NCP1612A1, NCP1612A3 and NCP1612B latch off if Vpin10 exceeds 7.5 V.

www.onsemi.com

7

Share Link: