MAX11044(2009) Просмотр технического описания (PDF) - Maxim Integrated

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MAX11044
(Rev.:2009)

4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs

Maxim Integrated 

4-/6-/8-Channel, 16-Bit,

Simultaneous-Sampling ADCs

Applications Information

Digital Interface

The bidirectional, parallel, digital interface, DB0–DB3,

sets the 4-bit configuration register. This interface

configures the following control signals: chip select

(CS), read (RD), write (WR), end of conversion (EOC),

and convert start (CONVST). Figures 6 and 7 and the

Timing Characteristics in the Electrical Characteristics

table show the operation of the interface. DB0–DB3,

together with the output-only DB4–DB15, also output

the 16-bit conversion result. All bits are high imped-

ance when RD = 1 or CS = 1.

DB3 (Int/Ext Reference)

DB3 selects the internal or external reference. The POR

default = 0.

0 = internal reference, REFIO internally driven through a

10kΩ resistor, bypass with 0.1µF capacitor to AGND.

1 = external reference, drive REFIO with a high-quality

reference.

DB2 (Output Data Format)

DB2 selects the output data format. The POR default = 0.

0 = offset binary.

1 = two’s complement.

Set to 0 for normal operation.

0 = normal operation.

1 = reserved; do not use.

DB1 (Reserved)

DB0 (CONVST Mode)

DB0 selects the acquisition mode. The POR default = 0.

0 = CONVST controls the acquisition and conversion.

Drive CONVST low to start acquisition. The rising edge

of CONVST begins the conversion.

1 = acquisition mode starts as soon as the previous

conversion is complete. The rising edge of CONVST

begins the conversion.

Programming the Configuration Register

To program the configuration register, bring the CS and

WR low and apply the required configuration data on

DB3–DB0 of the bus and then raise WR once to save

changes.

Table 1. Configuration Register

DB3

DB2

DB1

Int/Ext

Reference

Output

Data Format

Reserved

DB0

CONVST

Mode

Starting a Conversion

CONVST initiates conversions. The MAX11044/

MAX11045/MAX11046 provide two acquisition modes

set through the configuration register. Allow a quiet time

(tQ) of 500ns prior to the start of conversion to avoid

any noise interference during readout or write opera-

tions from corrupting a sample.

In default mode (DB0 = 0), drive CONVST low to place

the MAX11044/MAX11045/MAX11046 into acquisition

mode. All the input switches are closed and the internal

T/H circuits track the respective input voltage. Keep the

CONVST signal low for at least 1µs (tACQ) to enable

proper settling of the sampled voltages. On the rising

edge of CONVST, the switches are opened and the

MAX11044/MAX11045/MAX11046 begin the conversion

on all the samples in parallel. EOC remains high until

the conversion is completed.

In the second mode (DB0 = 1), the MAX11044/

MAX11045/MAX11046 enter acquisition mode as soon

as the previous conversion is completed. CONVST rising

edge initiates the next sample and conversion sequence.

CONVST needs to be low for at least 20ns to be valid.

Provide adequate time for acquisition and the requisite

quiet time in both modes to achieve accurate sampling

and maximum performance of the MAX11044/

MAX11045/MAX11046.

Reading Conversion Results

The CS and RD are active-low, digital inputs that con-

trol the readout through the 16-bit, parallel, 20MHz data

bus (D0–D15). After EOC transitions low, read the con-

version data by driving CS and RD low. Each low peri-

od of RD presents the next channel’s result. When CS

and RD are high, the data bus is high impedance. CS

may be driven high between individual channel read-

outs or left low during the entire 8-channel readout.

Reference

Internal Reference

The MAX11044/MAX11045/MAX11046 feature a preci-

sion, low-drift, internal bandgap reference. Bypass REFIO

with a 0.1µF capacitor to AGND to reduce noise. The

REFIO output voltage may be used as a reference for

other circuits. The output impedance of REFIO is 10kΩ.

Drive only high impedance circuits or buffer externally

when using REFIO to drive external circuitry.

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