MAX11046ECB-T Просмотр технического описания (PDF) - Maxim Integrated
Номер в каталоге
Компоненты Описание
производитель
MAX11046ECB-T Datasheet PDF : 28 Pages
| |||
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Starting a Conversion
CONVST initiates conversions. The MAX11044/MAX11044B
MAX11045/MAX11045B/MAX11046/MAX11046B and
MAX11054/MAX11055/MAX11056 provide two acquisition
modes set through the configuration register. Allow a quiet
time (tQ) of 500ns prior to the start of conversion to avoid
any noise interference during readout or write operations
from corrupting a sample.
In default mode (CR0 = 0), drive CONVST low to place the
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 into acquisition mode. All the input switches
are closed and the internal T/H circuits track the respective
input voltage. Keep the CONVST signal low for at least 1μs
(tACQ) to enable proper settling of the sampled voltages.
On the rising edge of CONVST, the switches are opened
and the MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 begin the conversion on all the samples in par-
allel. EOC remains high until the conversion is completed.
In the second mode (CR0 = 1), the MAX11044/
MAX11044B/MAX11045/MAX11045B/MAX11046/
MAX11046B and MAX11054/MAX11055/MAX11056
enter acquisition mode as soon as the previous conver-
sion is completed. CONVST rising edge initiates the
next sample and conversion sequence. CONVST needs
to be low for at least 20ns to be valid.
Provide adequate time for acquisition and the requisite
quiet time in both modes to achieve accurate sampling
and maximum performance of the MAX11044/
MAX11044B/MAX11045/MAX11045B/MAX11046/MAX1
1046B and MAX11054/MAX11055/MAX11056.
Reading Conversion Results
The CS and RD are active-low, digital inputs that con-
trol the readout through the 16-/14-bit, parallel, 20MHz
data bus (D0–D15/D13). After EOC transitions low, read
the conversion data by driving CS and RD low. Each
low period of RD presents the next channel’s result.
When CS or RD are high, the data bus is high imped-
ance. CS may be driven high between individual chan-
nel readouts or left low during the entire 8-channel
readout.
Reference
Internal Reference
The MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B and MAX11054/MAX11055/
MAX11056 feature a precision, low-drift, internal
bandgap reference. Bypass REFIO with a 0.1μF capaci-
tor to AGND to reduce noise. The REFIO output voltage
may be used as a reference for other circuits. The output
impedance of REFIO is 10kΩ. Drive only high impedance
circuits or buffer externally when using REFIO to drive
external circuitry.
External Reference
Set the configuration register to disable the internal ref-
erence and drive REFIO with a high-quality external ref-
erence. To avoid signal degradation, ensure that the
integrated reference noise applied to REFIO is less
than 10μV in the bandwidth of up to 50kHz.
CS
(USER SUPPLIED)
t5
t3
t4
WR
(USER SUPPLIED)
t7
t6
CR0–CR3
(USER SUPPLIED)
CONFIGURATION
REGISTER
Figure 4. Programming Configuration-Register Timing
Requirements
CS
(USER SUPPLIED)
RD
(USER SUPPLIED)
DB0–DB15/DB13
t8
t9
t10
t11
t12
t13
Sn
Sn + 1
Figure 5. Readout Timing Requirements
18
Maxim Integrated
Share Link: 