SAA7377GP Просмотр технического описания (PDF) - Philips Electronics
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SAA7377GP Datasheet PDF : 56 Pages
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Philips Semiconductors
Digital servo processor and Compact Disc
decoder (CD7)
Product specifications
SAA7377
W96
200 µs
min
11.3
µs
1 QR S T U VW
11.3 µs min
90 µs max
1Q
MGD038
Fig.8 Subcode format and timing on pin V4.
7.6 FIFO and error corrector
The SAA7377 has a ±8 frame FIFO. The error corrector is
a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols are
used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after (de-interleaving) by C2,
to help in the generation of C2 output flags.
The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM).
7.6.1 FLAGS OUTPUT (CFLG)
The flags output pin CFLG (open-drain) shows the status
of the error corrector and interpolator and is updated every
frame (7.35 kHz). In the SAA7377 chip a 1-bit flag is
present on the CFLG pin as illustrated in Fig.9. This signal
shows the status of the error corrector and interpolator.
The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
may also be used in a super FIFO or in the synchronization
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by register A.
handbook, full pagewidth
F8
33.9 µs
11.3
µs
F1 F2 F3 F4 F5 F6 F7 F8
33.9 µs
F1
MGD037
1998 Jul 06
Fig.9 Flag output timing diagram.
12
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