74LVQ74SCX(1998) Просмотр технического описания (PDF) - Fairchild Semiconductor

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74LVQ74SCX
(Rev.:1998)

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

Fairchild Semiconductor 

May 1998

74LVQ74

Low Voltage Dual D-Type Positive Edge-Triggered

Flip-Flop

General Description

The LVQ74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs. In-

formation at the input is transferred to the outputs on the

positive edge of the clock pulse. Clock triggering occurs at a

voltage level of the clock pulse and is not directly related to

the transition time of the positive-going pulse. After the Clock

Pulse input threshold voltage has been passed, the Data in-

put is locked out and information present will not be trans-

ferred to the outputs until the next rising edge of the Clock

Pulse input.

Asynchronous Inputs:

LOW input to SD (Set) sets Q to HIGH level

LOW input to CD (Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CD and SD makes both Q and Q

HIGH

Features

n Ideal for low power/low noise 3.3V applications

n Guaranteed simultaneous switching noise level and

dynamic threshold performance

n Guaranteed pin-to-pin skew AC performance

n Guaranteed incident wave switching into 75Ω

Ordering Code:

Order Number

74LVQ74SC

74LVQ74SJ

Package Number

M14A

M14D

Package Description

14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC

14-Lead Molded Small Outline Package, SOIC EIAJ

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

DS011347-1

DS011347-2

© 1998 Fairchild Semiconductor Corporation DS011347

DS011347-3

Connection Diagram

Pin Assignment

for SOIC JEDEC and EIAJ

DS011347-4

www.fairchildsemi.com

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