HEF4104BT,652 Просмотр технического описания (PDF) - NXP Semiconductors.
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HEF4104BT,652 Datasheet PDF : 14 Pages
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NXP Semiconductors
HEF4104B
Quad low-to-high voltage translator with 3-state outputs
a. Input waveforms
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
001aaj781
VI
G
VDD
VO
DUT
VEXT
RL
RT
CL
001aaj915
b. Test circuit
Fig 7.
Test data given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Test circuit for measuring switching times
Table 10. Test data
Supplies
Input
VDD(A) = VDD(B)
5 V to 15 V
tr, tf
≤ 20 ns
Load
RL
1 kΩ
CL
50 pF
VEXT
tPHL, tPLH
open
tPZL, tPLZ
VDD(B)
tPZH, tPHZ
VSS
HEF4104B_7
Product data sheet
Rev. 07 — 16 December 2009
© NXP B.V. 2009. All rights reserved.
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