HM-6551 Просмотр технического описания (PDF) - Intersil
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HM-6551 Datasheet PDF : 7 Pages
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Functional Diagram
HM-6551
A0
A
A1
LATCHED
5 GATED
A5
A6
ADDRESS
REGISTER A
ROW
DECODER
32
A7
5
32 x 32
MATRIX
D0
A
D1
A
D2
A
D3
A
8 8 8 8D
Q
GATED COLUMN
DECODER
AND DATA I/O
3
3
D DATA Q
D
OUTPUT
LATCHES
Q
D
Q
L
Q0
A
Q1
A
Q2
A
Q3
A
E
W
L
S2
D SELECT Q
LATCH
S1
A
A
LATCHED ADDRESS
REGISTER
A2
A3
A4
NOTES:
1. Select Latch: L Low → Q = D and Q latches on rising edge of L.
2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
3. All lines positive logic-active high.
4. Three-State Buffers: A high → output active.
5. Data Latches: L High → Q = D and Q latches on falling edge of L.
6-2
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