DRP3510A Просмотр технического описания (PDF) - Micronas

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DRP3510A

Digital Radio Processor

Micronas 

DRP 3510A

ADVANCE INFORMATION

6.4.2. PIO-DMA Mode

The PIO-DMA mode is selected by setting the corre-

sponding bit in the main configuration register 96. The

PIO-DMA mode gives access to the undecoded data,

which are simultaneously sent to the integrated MPEG

Layer 2 decoder. In this mode, PIO lines PI0..PI3 and

PI12..PI19 are switched to output. The PIO lines

PI12..PI19 will give an 8-bit parallel access to the bit

stream data. The data is always sent in packets of 16 by-

tes every 0.667 ms. The data are 8-bit aligned with MSB

first (at position PI19). The MPEG data are aligned in

such a way that the first bit of the MPEG header is always

positioned at the MSB (PI19) of the 8-bit word. In order

to read out the data stream, a special handshake proto-

col must be used (see Fig. 6–4).

The data transfer is started after the EODQ-pin of the

DRP is set to an active state. After checking this, the con-

troller requests data by activating the PR-line. The DRP

asserts that the first data word is placed on the bus by

generating a negative strobe impulse on PRTW. Now,

the controller may read the data word, and subsequent-

ly, it may request the next byte by activating the PR-line

again. This procedure will be repeated 16 times. After

the 17th PR impulse of the controller, the EODQ signal

of the DRP will be activated, which indicates that the

transfer of one data block has been finalized. The data

for one 16-byte block is transmitted in 0.6ms. However,

the complete protocol should be executed in less than

0.5 ms to avoid data loss. A description of timing details

can be found in section 12.1. This PIO-DMA mode will

not work in the E4 version (see also section 13).

6.5. The SP/DIF Interface

The SP/DIF interface generates a 48, 44.1, or 32 kHz

digital signal conforming to the IEC 958 consumer stan-

dard. In ADR mode, only 48 kHz sampling frequencies

are generated. The interface definition covers the data

stream and the physical timing specifications of the data

transmission. The transmission is done via the “bi-

phase-mark” code (Fig. 6–5).

The SP/DIF signal consists of 32-bit subframes. The first

4 bits are used for the sync impulse (Preambles). There

are three different sync signals: The first subframe nor-

mally starts with preamble “X”. However, the preamble

changes to preamble “Z” once every 192 frames. “Z”

also indicates the block begin, which is used to organize

the channel status information. The second subframe al-

ways starts with preamble “Y”. (see Fig 6–7). Two sub-

frames form one frame, 192 frames are collected into

one super-frame (or block). The preamble is followed by

4 auxiliary bits, which are not used in this application

(forced to 0), and 20 data bits. A subframe will be com-

pleted with the validity bit, user bit, channel status bit,

and parity bit (see Fig 6–6).

6.6. Copy Protection

The copy protection mode is set either according to the

incoming MPEG bit stream or explicitly to “no copy al-

lowed” regardless of the copy protection setting of the

MPEG bit stream. The copy protection mode is select-

able by setting bit 8 in the main configuration register. In

the default mode (bit 8 = 0), the copy bit of the MPEG bit

stream that is set by the service provider is directly eva-

luated to set the copy protection within the SPDIF output

bit stream. If copy protection is coded in the MPEG

header, one can record the program, but a further digital

copy of the recorded material is not allowed. If no copy

protection is coded in the MPEG header, a digital copy

is allowed. The copy protection can be forced regardless

of the copy protection setting in the MPEG bit stream by

setting the main configuration register (bit 8 = 1).

EODQ

PR

PRTW

PI12...19

Fig. 6–4: Handshake protocol for getting MPEG data via PIO-DMA

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