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C8051F536

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

C2CK/RST

VREGIN

VDD

GND

Power On

Reset

Reset

Debug /

Programming

Hardware

C2D

CIP-51 8051

Controller Core

up to 8k Byte Flash

Program Memory

256 Byte SRAM

Voltage Regulator

(LDO)

XTAL1

XTAL2

System Clock Setup

External Oscillator

Internal Oscillator

SFR

Bus

Port I/O Configuration

Digital Peripherals

UART0

Timers 0,

1, 2, 3

PCA/

WDT

Priority

Crossbar

Decoder

LIN 2.1

SPI

Crossbar Control

Analog Peripherals

VDD

Voltage

Reference VREF

VREF

12-bit

200ksps

ADC

VDD

A

VREF

M

U

Temp

X Sensor

GND

CP0, CP0A +

-

Comparator

VREGIN

Port 0

Drivers

Port 1

Drivers

P0.0/VREF

P0.1

P0.2

P0.3

P0.4/TX

P0.5/RX

P0.6/C2D

P0.7/XTAL1

P1.0/XTAL2

P1.1

P1.2/CNVSTR

P1.3

P1.4

P1.5

P1.6

P1.7

Figure 1.1. C8051F53xA/F53x-C Block Diagram

C2CK/RST

VREGIN

VDD

GND

Power On

Reset

Reset

Debug /

Programming

Hardware

C2D

CIP-51 8051

Controller Core

up to 8k Byte Flash

Program Memory

256 Byte SRAM

Voltage Regulator

(LDO)

XTAL1

XTAL2

System Clock Setup

External Oscillator

Internal Oscillator

SFR

Bus

Port I/O Configuration

Digital Peripherals

UART0

Timers 0,

1, 2, 3

PCA/

WDT

Priority

Crossbar

Decoder

LIN 2.1

SPI

Crossbar Control

Analog Peripherals

VDD

Voltage

Reference VREF

VREF

12-bit

200ksps

ADC

VDD

A

VREF

M

U

Temp

X

Sensor

GND

CP0, CP0A +

-

Comparator

VREGIN

Port 0

Drivers

P0.0/VREF

P0.1/C2D

P0.2/XTAL1

P0.3/XTAL2

P0.4/TX

P0.5/RX/

CNVSTR

Figure 1.2. C8051F52xA/F52x-C Block Diagram

16

Rev. 1.4

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