M34D64-W Просмотр технического описания (PDF) - STMicroelectronics

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производитель

M34D64-W

64 Kbit serial I²C bus EEPROM with hardware write control on top quarter of memory

STMicroelectronics 

Device operation

M34D64-W

Figure 7. Write mode sequences with WC = 0 (data write enabled)

WC

Byte Write

ACK

ACK

ACK

ACK

Dev sel

Byte addr

Byte addr

Data in

R/W

WC

Page Write

ACK

ACK

ACK

ACK

Dev sel

Byte addr

Byte addr

Data in 1

Data in 2

R/W

WC (cont'd)

Page Write

(cont'd)

ACK

ACK

Data in N

AI01106d

3.6

14/27

Write operations

Following a Start condition the bus master sends a Device Select Code with the Read/Write

bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7.: Write mode

sequences with WC = 0 (data write enabled), and waits for two address bytes. The device

responds to each address byte with an acknowledge bit, and then waits for the data byte(s).

Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write

instruction with Write Control (WC) driven high (during a period of time from the Start

condition until the end of the two address bytes) will not modify the contents of the top

quarter of the memory.

Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant

Byte (Table 3.: Most significant byte) is sent first, followed by the Least Significant Byte ( : ).

Bits b15 to b0 form the address of the byte in memory.

When the bus master generates a Stop condition immediately after the Ack bit (in the “10th

bit” time slot), either at the end of a Byte Write or a Page Write, the internal EEPROM Write

cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write

cycle.

During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does

not respond to any requests.

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